Texas Instruments Corporation

Gregory Raymond Shurtz

Mihir Narendra Mody

Sriramakrishnan Govindarajan

Jason A T Jones

Kedar Satish Chitnis

Charles Lance Fuoco

Amritpal Singh Mundra

Jonathan Elliot Bergsagel

Jayant Thakur

Daniel Brad Wu

Rajat Sagar

William A Mills

Abhishek Shankar

Santhanakrishnan Badri Narayanan

Donald Edward Steiss

Denis R Beaudoin

Anthony J Lell

Prithvi Shankar Yeyyadi Anantha

Kishon Vijay Abraham Israel Vijayponraj

Yashwant Dutt

Hemant Vijay Kumar Hariyani

Sanand Prasad

Mark Adrian Bryans

Soujanna Sarkar

Martin Jeffrey Ambrose

Robert John Tivy

Bradley Douglas Cobb

Niraj Nandan

Ajit Deepak Gupte

Veeramanikandan Raju

Brian Okchon Chae

Samuel Paul Visalli

Anish Reghunath

Denis Roland Beaudoin

Venkateswara Rao Mandela

Nishanth Menon

Rajesh Kumar Vanga

Sunita Nadampalli

Jason At Jones

Patrick Kruse

Anthony Joseph Lell

Narayanan Swaminathan

In described examples, a method of operating a system on chip (SoC) includes the following steps. Receive a component description that describes connections among circuit elements of the SoC. Receive a list of specified peripherals to activate while the SoC boots. Receive a hint data that describes a bypass mode clock frequency of a phase locked loop (PLL) of the SoC. Determine an operational data in response to the component description, the hint data, and the specified peripherals. The operational data specifies a subset of the circuit elements required to make the specified peripherals operational. Initialize, and limit the initializing, to the subset of the circuit elements.

Integrated circuit with accelerated boot to priority function

A hub that receives sensor data streams and then distributes the data streams to the various systems that use the sensor data. A demultiplexer (demux) receives the streams, filters out undesired streams and provides desired streams to the proper multiplexer (mux) or muxes of a series of muxes. Each mux combines received streams and provides an output stream to a respective formatter or output block. The formatter or output block is configured based on the destination of the mux output stream, such as an image signal processor, a processor, memory or external transmission. The output block reformats the received stream to a format appropriate for the recipient and then provides the reformatted stream to that recipient.

Flexible hub for handling multi-sensor data

This disclosure relates to various implementations an embedded computing system. The embedded computing system comprises a hardware accelerator (HWA) thread user and a second HWA thread user that creates and sends out message requests. The HWA thread user and the second HWA thread user is communication with a microcontroller (MCU) subsystem. The embedded computing system also comprises a first inter-processor communication (IPC) interface between the HWA thread user and the MCU subsystem and a second IPC interface between the second HWA thread user and the MCU subsystem, where the first IPC interface is isolated from the second IPC interface. The MCU subsystem is also in communication with a first domain specific HWA and a second domain specific HWA.

Safe, secure, virtualized, domain specific hardware accelerator

Arbitration and interleaving are performed with respect to memory requests in a memory controller that includes a set of interfaces, each configured to be coupled to a respective one of multiple external requestors, in which each interface receives memory requests from its associated external requestor. The memory controller further includes multiple sets of memory channel queues, one set for each interface, and multiple requestor arbitration modules, each associated with and coupled to a respective one of the multiple sets of memory channels. The memory controller further includes an interconnect coupled to the multiple requestor arbitration modules. The interconnect includes multiple external memory arbitration modules. Each of the requestor arbitration modules applies an arbitration algorithm to arbitrate among the memory requests in the associated set of memory channel queues. Each of the external memory arbitration modules also applies an arbitration algorithm to arbitrate among memory requests presented by the requestor arbitration modules.

Multichannel memory arbitration and interleaving scheme

Devices, systems and techniques for implementing freedom from interference (FFI) access rules. In an example, a device includes a set of primary components, a set of secondary components, and an interconnected coupled between the two sets of components. Each primary component of the set of primary components has an access identifier, among multiple access attributes, and an access attribute, among multiple access modes. Each secondary component of the set of secondary components is protected by a firewall. Each firewall is configured to specify, for each specific combination of an access identifier and access attribute, whether access to the associated secondary component is permitted and what type of access is permitted.

Method and system for freedom from interference (FFI)

An example apparatus includes: bandwidth estimator circuitry configured to: obtain a first memory transaction; and determine a consumed bandwidth associated with the memory transaction; and gate circuitry configured to: permit transmission of the memory transaction to a memory controller circuitry; determine whether to gate a second memory transaction generated by a source of the first memory transaction based on the consumed bandwidth of the first memory transaction; and when it is determined to gate the second memory transaction, prevent transmission of the second memory transaction for an amount of time based on the consumed bandwidth.

Methods and apparatus to estimate consumed memory bandwidth

A method of enabling memory access freedom from interference (FFI) rules, comprising: determining a first safety privilege access ID (PrivID) for a first component of a system (e.g., based on Automotive Safety Integrity Level (ASIL) attributes of tasks executed by the first component); determining a first access attribute for a first software task executing on the first component; receiving, at a first firewall component of the system, a request from the first software task to access a first memory region of a second component of the system, wherein the request specifies the first PrivID and the first access attribute; and determining, by the first firewall component, whether to permit the first software task to access the first memory region based on the first PrivID, the first access attribute, and the first memory region.

Techniques including a memory controller with a set of memory channel queues, wherein memory channel queues of the set of memory channel queues correspond to memory channels to access a set of memory modules, a first arbitration module, and a second arbitration module. The memory controller is configured to receive a first memory request from the peripheral and place one or more portions of the first memory request in the memory channel queues of the set of memory channel queues. The first arbitration module is configured to determine an arbitration algorithm, select a first memory channel queue based on the arbitration algorithm, present the one or more portions of the first memory request in the selected first memory channel queue to the second arbitration module, and output the presented one or more portions of the first memory request based on a selection by the second arbitration module.

An integrated circuit. The integrated circuit comprises an interconnect communication bus and a plurality of peripheral component interconnect (PCI) multi-function endpoints (MFN-EPs) coupled to the interconnect communication bus, each PCI MFN-EP comprising a multiplexing device, a first address translation unit (ATU), and at least one PCI function circuit, each PCI function circuit comprising another ATU and a plurality of base address registers (BARs).

Peripheral component interconnect (PCI) backplane connectivity system on chip (SoC)

An Ethernet switch and a switch microcontroller or CPU are integrated onto a system-on-a-chip (SoC). The Ethernet switch remains independently operating at full speed even though the remainder of the SoC is being reset or is otherwise nonoperational. The Ethernet switch is on a separated power and clock domain from the remainder of the integrated SoC. A warm reset signal is trapped by control microcontroller (MCU) to allow the switch CPU to isolate the Ethernet switch and save state. When the Ethernet switch is isolated and operating independently, the warm reset request is provided to the other entities on the integrated SoC. When warm reset is completed, the state is restored and the various DMA and flow settings redeveloped in the integrated SoC to allow return to normal operating condition.

Independent operation of an ethernet switch integrated on a system on a chip

An electronic device may be configured to detect a fault in imaging and vision hardware accelerators. The electronic device may include a controller configured to select a first golden input frame of multiple golden input frames to perform a first self-test, and retrieve a first reference image signature corresponding to the first golden input frame. The electronic device may include a hardware accelerator module configured to obtain the first golden input frame, and generate a first output frame based on the first golden input frame. The electronic device may include a signature generator configured to generate a first generated image signature based on the first output frame. The electronic device may include a signature comparison module configured to compare the first generated image signature to the first reference image signature in order to determine whether the hardware accelerator module includes a fault at a first time.

Permanent fault detection for imaging and vision hardware accelerators

In an example, a device includes a memory and a processor core coupled to the memory via a memory management unit (MMU). The device also includes a system MMU (SMMU) cross-referencing virtual addresses (VAs) with intermediate physical addresses (IPAs) and IPAs with physical addresses (PAs). The device further includes a physical address table (PAT) cross-referencing IPAs with each other and cross-referencing PAs with each other. The device also includes a peripheral virtualization unit (PVU) cross-referencing IPAs with PAs, and a routing circuit coupled to the memory, the SMMU, the PAT, and the PVU. The routing circuit is configured to receive a request comprising an address and an attribute and to route the request through at least one of the SMMU, the PAT, or the PVU based on the address and the attribute.

Real time input/output address translation for virtualized systems

Growing community of inventors

Houston, TX, United States of America

Gregory Raymond Shurtz