Seagate Technology Incorporated

Gregory Paul Moller

Hui Su

Steven Scott Williams

Jonathan Williams Haines

Brett Alan Cook

Xiong Liu

Timothy Richard Feldman

Wenxiang Xie

Paul Michael Wiggins

Michael J C Toh

Apparatus and method for managing a media cache through the monitoring of operational vibration of a data storage device. In some embodiments, a non-volatile media cache of the data storage device is partitioned into at least first and second zones having different data recording characteristics. Input data are received for storage in a non-volatile main memory of the data storage device. An amount of operational vibration associated with the data storage device is measured. The input data are stored in a selected one of the first or second zones of the media cache prior to transfer to the main memory responsive to a comparison of the measured amount of operational vibration to a predetermined operational vibration threshold.

Operational vibration compensation through media cache management

A method is provided for handling errors in a data storage system. The method includes determining a number of sectors to be accessed. Also, all sectors from the number of sectors are accessed during a first access routine. Next, error sectors are identified and the error sectors are accessed during a second access routine.

Data sector error handling mechanism

A method is provided for reducing growth errors in disc drive. First, a number of sectors to be read is determined. Data is then read from all sectors of the number of sectors on a disc during a first disc revolution. Next, error sectors having a number of errors above a predetermined threshold are identified. The error sectors are then corrected and written to the disc during a second disc revolution. In addition, a disc drive having a controller for implementing the above method is provided.

Data sector error tracking and correction mechanism

A method and system for managing the transfer of data into and out of a buffer in a disc drive is disclosed. The operation of the vectored buffer management (VBM) system is administered by a software-based control module. The control module creates and maintains a buffer table by dividing the buffer table into buffer sectors. The buffer sectors are further arranged into buffer segments, or circularly linked lists upon which the buffer table is partitioned. The control module effectuates the transfer by implementing an application module across the buffer table. Once the application module is arbitrarily positioned at an index sector by the control module, data transfer is accomplished when the application module walks through a particular buffer segment identified by the index sector. Specific control of the application module across a buffer segment is administered through host and disc address pointers, which are coupled to host and disc next pointers, respectively.

Buffer management system for managing the transfer of data into and out of a buffer in a disc drive

A disc sequencer incorporating parallel state machines to support both pipelined and non-pipelined read modes is disclosed. The parallel state machines include a first state machine and a second state machine for controlling whether data are read from a disc media and transferred to a buffer via a channel interface coupled to a read/write channel. Data may be read through the read/write channel in either pipelined or non-pipelined mode. If an operational state of either state machine is active, then the transfer of data between a read/write head accessing the media and the buffer is enabled. The operational state of the first state machine is dependent on the operational state of the second state machine such that if the second state machine is active, the operational state of the first machine will go active on the following clock period.

Disc sequencer supporting pipelined and non-pipelined read

The present invention relates generally to the field of disc controllers, and more specifically to an efficient buffer manager for a disc controller. A state machine in the buffer manager is provided which is responsive to a clock controlled by a single frequency base clock signal and a speed selection signal which indicates the speed of the buffer memory and which is designed to provide a base clock signal for the state machine having a fixed base period and an extended second portion of the cycle period which is extended to reflect the time of the RAMs cycle, plus the necessary time to allow for circuit delays and the like. Thus, different speed RAMs can be used in association with the buffer manager designed in this manner, while always controlling access for reading and writing to the RAM during a single complete cycle of the buffer manager. This allows for direct gating of all control signals to the buffer RAM, simplifying the design of the buffer memory controller and its associated logic. The buffer manager synchronizes all requests from various sources, and utilizes a single clock cycle of varying periods to accommodate all speeds of RAMs with just one base synthesizer frequency in order to reduce the cost and maximize simplicity oft he buffer manager design.

Single-cycle variable period buffer manager for disk controllers

The present invention relates generally to the field of disc controllers, and more specifically to an efficient buffer manager for a disc controller. A state machine in the buffer manager is provided which is responsive to a clock controlled by a single frequency base clock signal and a speed selection signal which indicates the speed of the buffer memory and which is designed to provide a base clock signal for the state machine having a fixed base period and an extended second portion of the cycle period which is extended to reflect the time of the RAMs cycle, plus the necessary time to allow for circuit delays and the like. Thus, different speed RAMs can be used in association with the buffer manager designed in this manner, while always controlling access for reading and writing to the RAM during a single complete cycle of the buffer manager. This allows for direct gating of all control signals to the buffer RAM, simplifying the design of the buffer memory controller and its associated logic. The buffer manager synchronizes all requests from various sources, and utilizes a single clock cycle of varying periods to accommodate all speeds of RAMs with just one base synthesizer frequency in order to reduce the cost and maximize simplicity of the buffer manager design.

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Longmont, CO, United States of America

Gregory Paul Moller