Intel Corporation

Gregory Mont Thornton

Bryon George Conley

Michael D Upton

Roland Pang

A method for indexing a cache includes searching on a cache index using a partial physical address, the partial physical address including any bits of the virtual address which are untranslated between the virtual address and the physical address. The partial physical address is used to identify a block of the cache index sets that might contain an address of requested data. The identification is performed prior to translation of the virtual address to the physical address. Once identified, the block is read out into an auxiliary memory structure. After the full physical address becomes available, the block is multiplexed down to one set, and a compare is performed on the ways of the set to determine if the requested data is in the cache and, if so, which way the data is in. A device for achieving the method includes a cache index organized into two arrays, each having a number of sets and a number of ways. One of the arrays may used to store micro-tags for way prediction. In addition, the device includes an auxiliary memory structure for receiving and storing intermediate search results.

Method and apparatus for indexing a cache

A memory system for providing rapid access to cached data includes a cache, a first TLB that stores address translation entries in a truncated form for fast access to data in the cache, and a second TLB that stores full address translation entries for accurate translation. The first TLB generates the tentative physical address quickly and initiates access to the cache using the tentative physical address. A way identified using the tentative physical address is read out of the cache and compared with a validated physical address provided by the second TLB. The initiated access is allowed to complete when the tentative and validated physical addresses match.

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Aloha, OR, United States of America

Gregory Mont Thornton