Intel Corporation

International Business Machines Corporation

Minebea Company, Limited

Gregory Martin Chrysler

Richard C Chu

Ioan Sauciuc

Robert E Simons

James G Maveety

Timothy M Anderson

Kramadhati V Ravi

Ravi S Prasher

Abhay A Watwe

Gary Franklin Goth

David Chau

Unnikrishnan Vadakkanmaruveedu

Chuan Hu

Michael C Garner

Sairam Agraharam

Yoshihiro Tomita

Je-Young Chang

Ravi V Mahajan

Shriram Ramanathan

Devendra Natekar

Dereje Agonafer

David T Vader

Chia-Pin Chiu

Fay Hua

Thomas Dory

Himanshu Pokharna

Edward Rudolph Prack

Tony A Opheim

Roger R Schmidt

Edward Joseph Seminaro

Eric DiStefano

Sarah E Kim

R Scott List

Kristopher J Frutschy

Jody A Hickey

Ajit V Sathe

Hakan Erturk

Willard S Harris

Agostino C Rinella

Leo Ofman

Jeffrey J Hare

Richard Chao-Fan Chu

Ward Scott

Daoqiang Lu

Saikumar Jayaraman

Alan M Myers

Paul J Gwin

Paul A Koning

Rajiv K Mongia

Rajashree Raji Baskaran

Carl L Deppisch

Gilroy J Vandentop

Javier Leija

Steven N Towle

Makarem A Hussein

Thomas John Fitzgerald

Patrick D Boyd

Jose Gonzalez

Pedro Chaparro Monferrer

Anna M George, Legal Representative

Yousef M Jarrah

Kris Frutschy

Patrick H Harper

Ryan Lei

Mohammad M Farahani

Shen Zhao

Glen Meadows

Richard M Koenig

Christopher Best

Hirofumi Shoji

Robert E Simmons

Thang Ngugen

Eduardo A Sanchez

A method and apparatus to minimize thermal impedance using copper on the die or chip backside. Some embodiments use deposited copper having a thickness chosen to complement a given chip thickness, in order to reduce or minimize wafer warpage. In some embodiments, the wafer, having a plurality of chips (e.g., silicon), is thinned (e.g., by chemical-mechanical polishing) before deposition of the copper layer, to reduce the thermal resistance of the chip. Some embodiments further deposit copper in a pattern of bumps, raised areas, or pads, e.g., in a checkerboard pattern, to thicken and add copper while reducing or minimizing wafer warpage and chip stress.

Apparatus to minimize thermal impedance using copper on die backside

A method for fabricating a microelectronic assembly including a built-in TEC, a microelectronic assembly including a built-in TEC, and a system including the microelectronic assembly. The method includes providing a microelectronic device, and fabricating the TEC directly onto the microelectronic device such that there is no mounting material between the TEC and the microelectronic device.

Microelectronic assembly including built-in thermoelectric cooler and method of fabricating same

The formation of electronic assemblies is described. In one embodiment, an electronic assembly includes a semiconductor die and a plurality of spaced apart nanotube structures on the semiconductor die. The electronic assembly also includes a fluid positioned between the spaced apart nanotube structures on the semiconductor die. The electronic assembly also includes a endcap covering the plurality of nanotube structures and the fluid, wherein the endcap is positioned to define a gap between the nanotube structures and an interior surface of the endcap. The endcap is also positioned to form a closed chamber including the working fluid, the nanotube structures, and the gap between the nanotube structures and the interior surface of the endcap.

Nanotube based vapor chamber for die level cooling

An embodiment of the present invention is a technique to fabricate a metal interconnect. A first metal trace is printed on a die attached to a substrate or a cavity of a heat spreader in a package to electrically connect the first metal trace to a power contact in the substrate. A device is mounted on the first metal trace. The device receives power from the substrate when the package is powered.

Flexible interconnect pattern on semiconductor package

A structure including a die with at least one via within a semiconductor portion of the die, the via being proximate to a hot spot. The via is at least partially filled with a heat-dissipating material and is also capable of absorbing heat from the hot spot.

Die having a via filled with a heat-dissipating material

A carbon nanotube (CNT) array is patterned on a substrate. The substrate can be a microelectronic die or a heat sink for a die. The patterned CNT array is patterned by using a patterned catalyst on the substrate to form the CNT array by growing. The patterned CNT array can also be patterned by using a patterned mask on the substrate to form the CNT array by growing. A computing system that uses the CNT array for heat transfer from the die is also used.

Process that includes assembling together first and second substrates the have respective first and second carbon nanotube arrays with geometrically complementary patterns

A method and apparatus for removing vapor inside a liquid pump at the start up operation of the pump. In addition, a method and apparatus for removing liquid inside a compressor at the start up operation of the compressor. The pump and compressor each include a sensor attached to them that determines the physical state (i.e., liquid or vapor) of a material inside the pump or compressor. If vapor is detected inside the pump, a thermoelectric module connected to the pump is powered to condense the vapor into a liquid. Likewise, if liquid is detected inside the compressor a heater connected to the compressor is powered to evaporate the liquid into a vapor. After the state of the material inside the pump or compressor is changed, the pump or compressor is powered up for operation in a cooling system.

Method and apparatus for two-phase start-up operation

Disclosed is a compact and integrated fan, pump, and heat exchanger system where air-cooling is performed via the fan, liquid cooling is performed via a pump, and heat exchange fins in thermal contact with a fluid channel act as a heat exchanger. Heated fluid is carried inside the fluid channel, where heat therein is conducted to the fins. The air flows around the outside surfaces of the fins so that the heat transfers from the heated fluid into the air stream.

Compact air-plus-liquid thermal management module

An integrated circuit is cooled by microarchitecture controlled Peltier effect cooling. In one embodiment, a temperature sensor thermally coupled to at least a portion of the integrated circuit of a die is adapted to provide an output as a function of the temperature of an integrated circuit portion. Operation of a thermoelectric cooler thermally coupled to the integrated circuit portion is controlled as a function of the sensor output, wherein a controller of the integrated circuit controls the thermal electric cooler. Other embodiments are described and claimed.

Microarchitecture control for thermoelectric cooling

An embodiment of the present invention is a technique to fabricate a cover assembly. A cover has a base plate and sidewalls attached to perimeter of the base plate. The sidewalls have a height. A plurality of devices is attached to underside of the base plate. The devices have length corresponding to the height such that the devices are sealed within the cover when the cover is attached to a surface.

Cooling devices in semiconductor packages

A method, apparatus and system with a semiconductor package including a microchimney or thermosiphon using carbon nanotubes to modify the effective thermal conductivity of an integrated circuit die.

Carbon nanotube micro-chimney and thermo siphon die-level cooling

A semiconductor die is constructed and arranged to have at least one conduit portion therein. At least a portion of the conduit portion is proximate to the localized area. The conduit portion is at least partially filled with a heat-dissipating material. The conduit portion absorbs heat from the localized area and dissipates at least a portion of the heat away from the localized area.

Micro-chimney and thermosiphon die-level cooling

Process of making carbon nanotube array that includes impregnating the carbon nanotube array with metal

Growing community of inventors

Chandler, AZ, United States of America

Gregory Martin Chrysler