Analog Devices,inc.

Analog Devices Global

Gregory M Yukna

Yosef Stein

James M Wilson

Joshua A Kablotsky

Christopher Mayer

Colm J Prendergast

Lewis F Lahr

Hazarathaiah Malepati

Andrew James Higham

In one example, there is disclosed herein a processor configured for interruptible atomic exclusive memory operations. For example, a load exclusive (LDEX) may be followed by a store exclusive (STREX), with the two together forming an atom. To facilitate timely handling of interrupts, the STREX operation is split into two parts. The STREX_INIT is not interruptible but has a determinate execution time because it takes a fixed number of clock cycles. The STREX_INIT sends the value out to the memory bus. It is followed by a STREX_SYNC operation that polls a flag for whether a return value is available. STREX_SYNC is interruptible, and methods are disclosed for determining whether, upon return from an interrupt, atomicity of the operation has been broken. If atomicity is broken, the instruction fails, while if atomicity is preserved, the instruction completes.

Interruptible store exclusive

Reducing pipeline stall between a compute unit and address unit in a processor can be accomplished by computing results in a compute unit in response to instructions of an algorithm; storing in a local random access memory array in a compute unit predetermined sets of functions, related to the computed results for predetermined sets of instructions of the algorithm; and providing within the compute unit direct mapping of computed results to related function.

Compute units using local luts to reduce pipeline stalls

An instruction-based parallel median filtering processor and method sorts in parallel each combination of pairs of inputs into greater and lesser values; determines from that sorting the minimum, maximum and median filter values of the inputs; processes one of those values and provides the processed value as an input; and applies an instruction for providing one of the values to the processing step, and at least one other instruction for enabling indication of at least one of the maximum, minimum, median filter values.

Instruction-based parallel median filtering

A programmable compute unit with an internal register with a bit FIFO for executing Viterbi code is configured to accumulate in the forward path the best-path to each state in an internal register and store the survivor trace back information bit for each state in each stage in a bit FIFO; and in the trace back, selecting the optimal best-path through the Viterbi trellis by tracing through the bit trace back information survivor bits beginning with the survivor bit of the last stage path; and generating in response to the Viterbi constrain length and a current bit FIFO address, the next bit FIFO address and decoded output bit for the next previous stage.

Programmable compute unit with internal register and bit FIFO for executing Viterbi code

Pipelined digital signal processor

Finite impulse response filtering is achieved by broadcasting to at least one compute unit an instruction having a plurality of data samples, a conditional field associated with each compute unit, and a set of operator values for operating on each data sample; providing a function of each the data sample in accordance with an associated set of operator values identified by the conditional field; and combining the functions to obtain an intermediate finite impulse response of the data samples.

Method and apparatus for accelerating processing of adaptive finite impulse response filtering

A method and apparatus for direct mapping in a compute unit having an internal random access memory the primary operational sequences of an algorithm to related function including storing in an internal random access memory at least one predetermined direct mapped function value for each primary operational sequence of an algorithm; holding in an input data register the address in the random access memory of at least one mapped function value for a selected primary operational sequence of the algorithm and holding in an output register the at least one mapped function value for the selected primary operational sequence of the algorithm read out of the random access memory.

Growing community of inventors

Norton, MA, United States of America

Gregory M Yukna