Motorola Corporation

Gregory M Yeric

Frank Kelsey Baker, Jr

Erwin J Prinz

Wei-Ming Chen

Kevin Yun-kang Wu

In one embodiment, the reliability of an integrated circuit having a floating gate device (50), a high breakdown voltage transistor (52), and a low breakdown voltage transistor (54), which are electrically isolated from each other by a trench isolation region (12), is improved by using an oxidation resistant layer (24). The oxidation resistant layer (24) protects portions of the trench isolation region (12) when the gate dielectric layer (30) for the high breakdown voltage transistor (52) is formed, and when the gate dielectric layer (36) for the low breakdown voltage transistor (54) is formed. The oxidation resistant layer (24) minimizes etching of the field isolation region (12) so that thinning or recessing of the field isolation region (12) is minimized.

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Dallas, TX, United States of America

Gregory M Yeric