Memc Electronic Materials, Inc.

Gregory M Wilson

Jon A Rossi

Charles C Yang

Thomas A Torack

Charles Robert Lottes

Michael John Ries

Andrei Stefanescu

Jiri L Vasat

A wafer is characterized in that the wafer has a non-uniform distribution of crystal lattice vacancies, wherein the concentration of crystal lattice vacancies in the bulk layer are greater than the concentration of crystal lattice vacancies in the front surface layer. In addition, the front surface of the wafer has an epitaxial layer, having a thickness of less than about 2.0 &#xe7;m, deposited thereon. A process comprises heating a surface of a wafer starting material to remove a silicon oxide layer from the surface and depositing an epitaxial layer onto the surface to form an epitaxial wafer. The epitaxial wafer is then heated to a soak temperature of at least about 1175C. while exposing the epitaxial layer to an oxidizing atmosphere comprising an oxidant, and the wafer is cooled at a rate of at least about 10C./sec.

Epitaxial silicon wafer with intrinsic gettering and a method for the preparation thereof

A process for manufacturing silicon wafers that reduces the size of silicon wafer surface and/or sub-surface defects without the forming excessive haze. The process entails cleaning the front surface of the silicon wafer at a temperature of at least about 1100&deg; C. by exposing the front surface to a cleaning ambient comprising H , HF gas, or HCl gas to remove silicon oxide from the front surface and exposing the cleaned front surface of the silicon wafer at a temperature of at least about 1100&deg; C. to a vacuum or an annealing ambient consisting essentially of a mono-atomic noble gas selected from the group consisting of He, Ne, Ar, Kr, and Xe to facilitate the migration of silicon atoms to the exposed agglomerated defects without substantially etching silicon from the front surface of the heated silicon wafer.

Thermal annealing process for producing silicon wafers with improved surface characteristics

This invention is directed to a novel a single crystal silicon wafer. In one embodiment, this wafer comprises: (a) two major generally parallel surfaces (i.e., the front and back surfaces); (b) a central plane between and parallel to the front and back surfaces; (c) a front surface layer which comprises the region of the wafer extending a distance of at least about 10 &mgr;m from the front surface toward the central plane; and (d) a bulk layer which comprises the region of the wafer extending from the central plane to the front surface layer. This wafer is characterized in that the wafer has a non-uniform distribution of crystal lattice vacancies, wherein (a) the concentration of crystal lattice vacancies in the bulk layer are greater than the concentration of crystal lattice vacancies in the front surface layer, (b) the crystal lattice vacancies have a concentration profile in which the peak density of the crystal lattice vacancies is at or near the central plane, and (c) the concentration of crystal lattice vacancies generally decreases from the position of peak density toward the front surface of the wafer. In addition, the front surface of the wafer has an epitaxial layer deposited thereon. This epitaxial layer has a thickness of from about 0.1 to about 2.0 &mgr;m.

This invention is directed to a novel a single crystal silicon wafer. The wafer comprises: (a) two major generally parallel surfaces (ie., the front and back surfaces); (b) a central plane between and parallel to the front and back surfaces; (c) a front surface layer which comprises the region of the wafer extending a distance of at least about 10 &mgr;m from the front surface toward the central plane; and (d) a bulk layer which comprises the region of the wafer extending from the central plane to the front surface layer. This wafer is characterized in that the wafer has a non-uniform distribution of crystal lattice vacancies, wherein (a) the concentration of crystal lattice vacancies in the bulk layer are greater than the concentration of crystal lattice vacancies in the front surface layer, (b) the crystal lattice vacancies have a concentration profile in which the peak density of the crystal lattice vacancies is at or near the central plane, and (c) the concentration of crystal lattice vacancies generally decreases from the position of peak density toward the front surface of the wafer. In addition, the front surface of the wafer has an epitaxial layer deposited thereon. The epitaxial layer has an average light scattering event concentration of no greater than about 0.06/cm,as measured by a laser-based auto inspection tool configured to detect light scattering events corresponding to polystyrene spheres having diameters of no less than about 0.12 &mgr;m. The bulk layer comprises voids which are at least about 0.01 &mgr;m in their largest dimension.

Epitaxial silicon wafer with intrinsic gettering

A system for equalizing pressure across a gate adapted to selectively block a port connecting a wafer handling chamber to a process chamber of a reactor for depositing an epitaxial layer on a semiconductor wafer positioned in the process chamber. The system comprises a bypass passage connecting the process chamber to the wafer handling chamber for transporting gas between the process chamber and the wafer handling chamber when the gate is blocking the port connecting the wafer handling chamber to the process chamber of the reactor for equalizing pressure between the process chamber and the wafer handling chamber. The system also includes a bypass valve positioned along the bypass passage for selectively controlling gas flow through the bypass passage. The bypass valve has an open position in which gas is permitted to flow through the bypass passage to equalize pressure between the process chamber and the wafer handling chamber and a closed position in which gas is prevented from flowing through the bypass passage to isolate the process chamber from the wafer handling chamber. In addition, the system includes a flow restrictor positioned along the bypass passage for restricting gas flow through the bypass passage to limit pressure change rates in the process chamber and the wafer handling chamber when the bypass valve is in the open position and thereby to limit a maximum velocity of gas flowing through the bypass passage.

Pressure equalization system for chemical vapor deposition reactors

A low pressure in situ wafer cleaning process and apparatus are disclosed wherein a low pressure external combustion reactor 2 in combination with a low pressure furnace 14 produces a stream of a combustion product through the combustion of a halogenated hydrocarbon and oxygen. The combustion product is contacted with semiconductor wafers in the low pressure furnace to remove Group I and II metals. After a sufficient time has passed for cleaning, the combustion reactor and furnace are purged with an inert gas to remove the combustion product. In a preferred embodiment, the halogenated hydrocarbon is trans-1,2-dichloroethylene and the combustion product is vaporous hydrochloric acid.

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Chesterfield, MO, United States of America

Gregory M Wilson