Digital Equipment Corporation

Avici Systems, Inc.

Juniper Networks, Inc.

Future Wei Technologies, Inc.

Gregory M Waters

William James Dally

Philip P Carvey

William Frederick Mann, Iii

Larry R Dennison

Robert J Simcoe

Charles W Kaufman

Avanindra Godbole

William R Hawe

Barry A Spinney

Jainendra Kumar

Amar Gupta

Cuneyt M Ozveren

Joseph J Tardo

Hallam G Murray, Jr

Raymond G Stephany

An output circuit, included in a device, may determine counter information associated with a packet provided via an output queue managed by the output circuit. The output circuit may determine that a latency event, associated with the output queue, has occurred. The output circuit may provide the counter information and time of day information associated with the counter information. The output circuit may provide a latency event notification associated with the output queue. An input circuit, included in the device, may receive the latency event notification associated with the output queue. The input circuit may determine performance information associated with an input queue. The input queue may correspond to the output queue and may be managed by the input circuit. The input circuit may provide the performance information associated with the input queue and time of day information associated with the performance information.

Monitoring packet residence time and correlating packet residence time to input sources

Prefix searches for directing internet data packets are performed in a prefix search integrated circuit. The integrated circuit includes an array of search engines, each of which accesses a prefix search tree data structure to process a prefix search. An SDRAM is dedicated to each search engine, and SDRAMs share address and control pins to plural search engines on the IC chip. Internal nodes of the tree data structure are duplicated across banks of the SDRAMs to increase bandwidth, and leaf nodes are stored across the SDRAM banks to reduce storage requirements. Within each search engine, data stored in a data register from an SDRAM is compared to a prefix search key stored in a key register. Based on that comparison, an address is calculated to access further tree structure data from the SDRAM. Packet descriptors containing search keys are forwarded to the search engines from an input queue and the search results are forwarded to an output queue, the same packet order being maintained in the two queues.

Prefix search circuitry and method

Prefix search method

A list of prefix keys, including enclosing prefix key pairs, are stored in leaves of a tree structure. In the leaf nodes, a prefix search key is compared to a set of prefix keys to identify a longest matching prefix. Each leaf node includes a single result pointer to a block of results and a single enclosing pointer to a result in a block of results for another node. Internal nodes which point to subsequent nodes include partitioning nodes and table nodes. In each partitioning node, a prefix search key is compared to a set of prefix keys which point to subsequent nodes through a common pointer and an index. Within each node, a middle prefix key is stored ahead of sets of high and low prefixes.

Apparatus and method for efficient prefix search

Prefix searches for directing internet data packets are performed in a prefix search integrated circuit. The integrated circuit includes an array of search engines, each of which accesses a prefix search tree data structure to process a prefix search. An SDRAM is dedicated to each search engine, and SDRAMs share address and control pins to plural search engines on the IC chip. Internal nodes of the tree data structure are duplicated across banks of the SDRALMs to increase bandwidth, and leaf nodes are stored across the SDRAM banks to reduce storage requirements. Within each search engine, data stored in a data register from an SDRAM is compared to a prefix search key stored in a key register. Based on that comparison, an address is calculated to access further tree structure data from the SDRAM. Packet descriptors containing search keys are forwarded to the search engines from an input queue and the search results are forwarded to an output queue, the same packet order being maintained in the two queues.

A flow control system is disclosed, for a transmitting node and a receiving node. The transmitting node and the receiving node are linked together through multiple connections or virtual circuits. A flow control circuit in the transmitting node limits the number of data transmission units transmitted from the transmitting station, and not yet copied out of the receive buffers in the receiving node, to the total number of receive buffers in the receiving node. The flow control circuit in the transmitting node further controls the transmission of data transmission units on the multiple connections fairly, such that all connections are provided a proportional amount of the total available receive buffers in the receiving node. In an example embodiment, a global counter is used to maintain the total number of receive buffers containing data in the receiving node, and a global limit register contains the maximum number of receive buffers containing data in the receiving node allowed for a single connection. The flow control circuit further includes logic providing fair and efficient allocation of receive buffers across all virtual circuits between a transmitting node and a destination node. The flow control circuit ensures that during steady state operation, receive buffers in the receiving node, which are used to store data transmission units received from the transmitting node, are fairly divided among all active virtual circuits in the transmitting node.

Flow control with smooth limit setting for multiple virtual circuits

A method and related cryptographic processing apparatus for handling information packets that are to be cryptographically processed prior to transmission onto a communication network, or that are to be locally cryptographically processed and looped back to a node processor. A special cryptographic preamble is included in each information packet that is to be subject to cryptographic processing. The cryptographic preamble contains an offset value pointing to the starting location of information that is to be processed, and completely defines the type of cryptographic processing to be performed. The cryptographic processor can then perform the processing as specified in the preamble without regard to a specific protocol. If the packet is to be transmitted onto the network, the preamble is stripped from the packet after cryptographic processing, so that the formats of packets transmitted onto the network will be unaffected by the preamble. Cryptographic processing modes include encryption of data for outbound transmission, encryption of a cipher key for loopback to the node processor, encryption or decryption of data for loopback to the node processor, and computation of an integrity check value for loopback to the node processor.

Generic encryption technique for communication networks

A digital communications system includes a transmitting section that receives electrical signals in parallel and transmits them serially by means of an optic fiber (10) to a receiving section (11). A sampler/filter (20) samples the incoming electrical signals at a rate several times that of the maximum data rate expected of those signals and employs majority-vote circuits (116) to change the value of any samples that are not part of a plurality of sequential samples of the same value. The achieve as balanced a signal as possible, a complementing unit (36) complements alternate groups of bits, and a coding unit (40) imposes a 4-to-5 code in which the code-word imbalances for complementary data words are opposite in the majority of cases. A serializing unit (44) serializes the resulting codewords, which an electrical-to-optical converter (8) transmits over the optic fiber (10) to the receiving section (11), which performs operations the reverse of those performed by the transmitting section (3) so as to forward parallel electrical signals.

Technique for organizing and coding serial binary data from a plurality

A data link (1000) multiplexes a large number of concurrently operating channel onto a single pair of fiber-optic cables (10 and 1010). A receiver (1004A) at one end of the links determines whether it is in sychronism with the signals that it receives over one of the cables (1010), and a transmitter (1002A) includes the result of that determination with the data that it sends to the other end if the link so that devices at the other end of the link can be caused to log off in response to extended lapses in synchronism at the first end. Each transmitter also sends an error count to the other end, and is responsive to a mode signal from the other end to reduce its signal power, so that maintenance personnel can perform many testing and diagnostic procedures from a single end of the link. A single integrated-circuit chip (1005A) receives data serially from a modularly expandable shift register (208) that has recieved the data in parallel, and the chip sends the data serially in a 'reverse' order so that expansion of the shift-register length requires no change in the chip.

Growing community of inventors

Groton, MA, United States of America

Gregory M Waters