Massachusetts Institute of Technology

Intel Corporation

Ergo Computing, Inc.

A.i. Architects, Inc.

Gregory M Papadopoulos

Michael J Keith

David L Sprague

Kevin Harney

Allen H Simon

Eiichi Kowashi

Arvind

Walter P Hays

Shih-Wei Shiue

George F Salem

Vitaly H Shilman

Anthony P Bertapelli

David E Culler

Rishiyur S Nikhil

Kim Molvig

Robert J Greiner

Richard P Schneider

James T Pinkerton

Data processing system with synchronization coprocessor for multiple

A system and method for arbitrating among memory requests. According to a preferred embodiment, the system comprises a global memory and a plurality of datapaths. Each datapath comprises a datapath processor for executing instructions of an instruction sequence and for providing a plurality of memory request signal types in accordance with the instructions, wherein the plurality of memory request signal types comprises instruction memory request signals, scalar memory request signals, first-in and first-out memory request signals, statistical decoder memory request signals, and block transfer memory request signals. Each datapath also comprises local memory, a global port for transferring data between the local memory and the global memory, and a dual port comprising first and second local ports for transferring data between the local memory and the datapath processor, wherein the first and second local ports permit simultaneous transfer of data between the local memory and the datapath processor. The system comprises a data bus coupled to the global memory for transferring data to and from the global memory, and a transfer controller for controlling block transfer and scalar data transfers between the local memory and the global memory over the data bus and for arbitrating among competing datapaths of the plurality of datapaths to grant to a selected datapath access to the data bus in accordance with the signal types of the memory request signals generated by datapaths of the plurality of datapaths.

System for controlling arbitration using the memory request signal types

A method and apparatus for processing data. According to a preferred embodiment, the apparatus comprises a plurality of datapaths, each datapath comprising datapath processor, and a statistical decoder input channel device. The statistical decoder input channel device prefetches variable length encoded data from a variable length encoded data source in response to a request by a program running on a datapath processor of a datapath of the plurality of datapaths. The statistical decoder input channel device comprises a statistical decoder processor and memory for decoding the variable length encoded data to provide fixed length decoded data, and a transmission output channel for transmitting the fixed length decoded data to the datapath.

System with plurality of datapaths having dual-ported local memory

A system and method for processing data. According to a preferred embodiment, the system comprises a global memory and a plurality of datapaths. Each datapath comprises a datapath processor for executing instructions of an instruction sequence and for providing a plurality of memory request signal types in accordance with the instructions, local memory, a global port for transferring data between the local memory and the global memory, and a dual port comprising first and second local ports for transferring data between the local memory and the datapath processor, wherein the first and second local ports permit simultaneous transfer of data between the local memory and the datapath processor. The system comprises a data bus coupled to the global memory for transferring data to and from the global memory, and a transfer controller for controlling block transfer and scalar data transfers between the local memory and the global memory over the data bus and for arbitrating among competing datapaths of the plurality of datapaths to gram to a selected datapath access to the data bus in accordance with the signal types of the memory request signals generated by datapaths of the plurality of datapaths.

Fluid flow is simulated by a massively parallel data processor having combinational logic for processing collision rules at lattice sites. Following collision processing, particle representations are moved to different sites dependent on direction and velocity of the particles. The collision rules are based on collisions of particles positioned at sites of a three-dimensional lattice. Particle representations identify particles of plural energy levels, and the collision rules allow for transfer of energy between particles. Particle representations relate to particles which move along four-dimensional face-centered hypercube lattices which project to the three-dimensional lattice. The lattice may include interfacing grids of different unit dimensions depending on the resolution required in individual volumes of space.

Particle interaction processing system

A multiprocessor system comprises a plurality of processing nodes, each node processing multiple threads of computation. Each node includes a data processor which sequentially processes blocks of code, each block defining a thread of computation. The code includes instructions to send start messages with data values to start new threads of computation. Each node also includes a synchronization coprocessor for processing start messages from the same and other nodes of the system. The coprocessor processes the start messages to store values as operands for threads of computation, to determine when all operands required for a thread of computation have been received and to provide an indication to the data processor that a thread of computation may be initiated. The data processor subsequently nonsynchronously initiates the thread of computation. Preferably, the processors load and store from and to a common memory with the translation from a local virtual address to a local physical address. The data processor creates messages to remote nodes using a global virtual address which is translated before transmission to a node designation and a local virtual address at the remote node. The synchronization coprocessor is a pipeline processor in which a data cache stage is modified to increment and test a counter value during a join operation.

A program is first analyzed in an ideal environment that assumes infinite processing resources and zero communication latency. In this environment, the program is viewed as being comprised of a plurality of steps of computation. Each step of computation is defined as the set of instructions that have all their operands available at that time. As such, each step of computation is limited only by data dependencies. The number of instructions executed for each step of computation is counted by the data processing system. The count of instructions may be used to produce an ideal parallelism profile that produces a graphical representation of the simulation. Having established an ideal level of parallelism in the ideal environment, a more realistic profile of the maximum level of parallelism may be obtained through analusis that accounts for a finite number of processors and for communication latency. This more realistic simulation is compared to the actual level of parallelism experienced when the program is executed. Should the comparison reveal room for improvement the program is tuned to resolve problems of work distribution and contention. of processors that process tokens; comprising the step of:

Efficient data processor instrumentation for systematic program

In a data processing system, multiple requests for a service are stored on a deferred list formed out of already allocated memory space. Specifically, a received service request is added to the deferred list by altering the request as dictated by a stated convention. Preferably, the convention mandates that an instruction pointer of the received service request is decremented or otherwise manipulated. The altered received service request then is exchanged for a sevice request currently held at the service. The altering and exhanging are performed atomically. The service request that was previously held for the service is sent to the head of the current deferred list. It is preferred that the deferred list be formed out of activation frames.

System and method for construction of lists of deferred service requests

A data flow processing system has a plurality of processing elements and memory units. Communication amongst processing elements and amongst processing elements and memory units is facilitated by an interconnection network. Each processing element is pipelined. The system operates upon data objects known as tokens. The tokens initiate activity within the processing element pipelines. Included within the activities initiated by the tokens is execution of instructions. Operands for instructions are matched in non-associative portions of memory known as activation frames. The activation frame memory locations have a state field that indicates whether a value is present or not in the activation frame. The state field may also indicate other information about an activation frame memory location. The state field is used to determine what action is taken at an activation frame memory location when an instruction is executed. The state field also determines the scheduling of execution of instructions. Moreover, the state field may be manipulated independent of a value held at an activation frame memory location.

Tagged token data processing system with operand matching in activation

A vector processor is closely integrated with a scalar processor. The scalar processor provides virtual-to-physical memory translation for both scalar and vector operations. In vector operations, a block move operation preformed by the scalar processor is intercepted, the write command in the operation is converted to a read, and data resulting from a vector operation is returned to the address specified by the block move write command. Writing of the data may be masked by a prior vector operation. Prefetch queues and write queues are provided between main memory and the vector processor. A microinstruction interface is supported for the vector processor.

Integrated scalar and vector processors with vector addressing by the

An electronic device comprising a state machine is coupled between the ROM and its socket. When armed by an arming sequence, the device responds to an address from a microprocessor during a reset operation to modify the output of the ROM. The modified output causes a jump to a routine in RAM rather than a jump in an initialization routine in the ROM. This enables a user to change the microprocessor's addressing mode from protected to real without a complete initialization of the system. Arming of the device and reset of microprocessor is caused by a protected mode routine, and after reset the mircroprocessor processes a real mode routine.

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Burlington, MA, United States of America

Gregory M Papadopoulos