Intel Corporation

Gregory M Iovino

Jiangtao Li

Hung-Piao Ma

Tawfik Arabi

Sanu K Mathew

Stephen H Gunther

Nasser A Kurd

Gregory F Taylor

Wei Wu

Mohammad Mamunur Rashid

Kevin Gotze

Shai Rotem

Avner Kornfeld

David Johnston

Patrick Koeberl

George W Cox

Rachael Jade Parker

Anand Rajan

Narasimha Lanka

Michael C Rifani

Benson D Inkley

Monib Ahmed

Eric Fetzer

Matthew C Reilly

Roman Rechter

Embodiments of an invention for using dark bits to reduce physically unclonable function (PUF) error rates are disclosed. In one embodiment, an integrated circuit includes a PUF cell array and dark bit logic. The PUF cell array is to provide a raw PUF value. The dark bit logic is to select PUF cells to mark as dark bits and to generate a dark bit mask based on repeated testing of the PUF cell array.

Dark bits to reduce physically unclonable function error rates

A method, of an aspect, includes challenging a set of Physically Unclonable Function (PUF) cells, of an integrated circuit device, and receiving a set of PUF bits from the PUF cells in response. A PUF key is generated based on the set of PUF bits. An encryption of the PUF key with an embedded key is output from the integrated circuit device. The integrated circuit device receives an encryption of a fuse key with the PUF key. Fuses of the integrated circuit device are programmed with at least one of the fuse key and the received encryption of the fuse key with the PUF key. Other methods, apparatus, and systems are also disclosed.

Secure provisioning of secret keys during integrated circuit manufacturing

An integrated circuit substrate of an aspect includes a plurality of exposed electrical contacts. The integrated circuit substrate also includes an inaccessible set of Physically Unclonable Function (PUF) cells to generate an inaccessible set of PUF bits that are not accessible through the exposed electrical contacts. The integrated circuit substrate also includes an accessible set of PUF cells to generate an accessible set of PUF bits that are accessible through the exposed electrical contacts. Other apparatus, methods, and systems are also disclosed.

Integrated circuits having accessible and inaccessible physically unclonable functions

Embodiments of an invention for fuse attestation to secure the provisioning of secret keys during integrated circuit manufacturing are disclosed. In one embodiment, an apparatus includes a storage location, a physically unclonable function (PUF) circuit, a PUF key generator, an encryption unit, and a plurality of fuses. The storage location is to store a configuration fuse value. The PUF circuit is to provide a PUF value. The PUF key generator is to generate a PUF key based on the PUF value. The encryption unit is to encrypt the configuration fuse value using the PUF key. The PUF key and the configuration fuse value are to be provided to a key server. The key server is to determine that the configuration fuse value indicates that the apparatus is a production component, and, in response, provide a fuse key to be stored in the plurality of fuses.

Fuse attestation to secure the provisioning of secret keys during integrated circuit manufacturing

Systems for testing a plurality of integrated circuits at a plurality of frequencies and voltages is disclosed. In one embodiment, a plurality of integrated circuits is tested at least once within a predetermined set of combinations of frequencies and voltages. If the integrated circuit fails testing within any combination of a frequency and voltage within the predetermined set, the integrated circuit is retested at a different predetermined set of combinations of frequencies and voltages. If the integrated circuit fails testing within any combination of a frequency and voltage within the different predetermined set, the integrated circuit is discarded.

Arrangements having IC voltage and thermal resistance designated on a per IC basis

A JTAG-compatible device includes a unique identifier stored in dedicated non-volatile memory, a test access port (TAP) controller, a TAP instruction register, a dedicated data register, and a comparison block. The TAP instruction register enables and/or disables TAP instruction execution by the device. The dedicated data register is of a length that is the same or a subset of the length of the unique identifier. The comparison block can be an arithmetic logic unit (ALU) or other circuitry that compares a code scanned into the dedicated data register with the unique identifier stored in a PROM. The TAP controller can selectively ignore TAP commands if a code scanned into dedicated data register does not match the stored unique identifier. This allows the TAP controller to conditionally or independently control several devices that are connected in parallel. The unique identifier can be device-specific, device type-specific, and/or device configuration specific.

Method and apparatus for independent control of devices under test connected in parallel

An on-die temperature control variable is provided to throttle a thermal actuator for cooling an integrated circuit. The integrated circuit includes a storage element to hold the temperature control variable. A temperature sensor is thermally coupled to the integrated circuit to sense an operating temperature of the integrated circuit. A thermal controller is communicatively coupled to the storage element and to the temperature sensor. The thermal controller throttles the thermal actuator when the temperature sensor indicates that the operating temperature of the integrated circuit is below the temperature control variable.

On-die temperature control data for communicating to a thermal actuator

Arrangements having integrated circuit (IC) voltage and thermal resistance designated on a per IC basis.

Testing arrangement to distribute integrated circuits

Growing community of inventors

Hillsboro, OR, United States of America

Gregory M Iovino