Qualcomm Incorporated

Gregory Lynch

Thomas Clark Bryan

Luverne Ray Peterson

Alvin Leng Sun Loke

Tin Tin Wee

Stephen Knol

Yue Li

Reza Jalilizeinali

Chiew-Guan Tan

Sreeker Dundigal

Jacob Schneider

Mohammed Mizanur Rahman

Wen-Yi Chen

Krishna Chaitanya Chillara

Rohit Shetty

An ESD protection circuit has a driver transistor with a drain that is coupled to an I/O pad of an IC device and a source that is coupled to a first rail of a power supply in the IC device, and a diode that couples the I/O pad to the first rail and that is configured to be reverse-biased when a rated voltage is applied to the I/O pad. The rated voltage lies within a nominal operating range for voltage levels defined for the input/output pad. The ESD protection circuit has a gate pull transistor that couples a gate of the driver transistor to the I/O pad or the first rail. The gate pull transistor may be configured to present a high impedance path between the gate of the driver transistor and the I/O pad or the first rail when the rated voltage is applied to the I/O pad. The gate pull transistor may be configured to provide a low impedance path between the gate of the driver transistor and the I/O pad or the first rail when an overvoltage signal applied to the I/O pad has a magnitude that exceeds the nominal operating range of voltage levels defined for the I/O pad.

Interface circuit with robust electrostatic discharge

Certain aspects of the present disclosure generally relate to a level-shifting circuit. The level-shifting circuit generally includes a first pull-up path having at least one first diode and at least one first transistor, and a second pull-up path having at least one second diode and at least one second transistor. The level-shifting circuit may also include a first pull-down path having a third transistor and a fourth transistor, wherein the fourth transistor is coupled between the third transistor and the first diode; a second pull-down path having a fifth transistor and a sixth transistor, wherein the sixth transistor is coupled between the fifth transistor and the second diode; and an overvoltage protection circuit coupled to gates of the fourth transistor and the sixth transistor.

Level shifter with auto voltage-bias reliability protection

A programmable equalizer and related method are provided. The equalizer includes a pair of current-setting field effect transistors (FETs) coupled in series with a pair of input FETs and a pair of load resistors, respectively, between a first voltage rail (Vdd) and a second voltage rail (ground). A programmable equalization circuit is coupled between the sources of the input FETs, comprising a plurality of selectable resistive paths and a variable capacitor, which could also be configured as a plurality of selectable capacitive paths. Each of the selectable resistive paths (as well as each of the selectable capacitive paths) include a selection FET for selectively coupling the corresponding resistive (or capacitive) path between the sources of the input FETs. In the case where one of the input FETs is biased with a reference gate voltage, the source of each selection FET is coupled to the source of such input FET.

Programmable high-speed equalizer and related method

Circuits for die-to-die clock distribution are provided. A system includes a transmit clock tree on a first die and a receive clock tree on a second die. The transmit clock tree and the receive clock tree are the same, or very nearly the same, so that the insertion delay for a given bit on the transmit clock tree is the same as an insertion delay for a bit corresponding to the given bit on the receive clock tree. While there may be clock skew from bit-to-bit within the same clock tree, corresponding bits on the different die experience the same clock insertion delays.

Systems and methods for clock distribution in a die-to-die interface

A circuit includes a first die having a first array of exposed data nodes, and a second die having a second array of exposed data nodes, wherein a given data node of the first array corresponds to a respective data node on the second array, further wherein the first array and the second array share a spatial arrangement of the data nodes, wherein the first die has data inputs and sequential logic circuits for each of the data nodes of the first array on a first side of the first array, and wherein the second die has data outputs and sequential logic circuits for each of the data nodes of the second array on a second side of the second array, the first and second sides being different.

Systems and methods for providing data channels at a die-to-die interface

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San Diego, CA, United States of America

Gregory Lynch