Seagate Technology Incorporated

Broadcom Corporation

Avago Technologies General IP (singapore) Pte. Ltd.

Gregory Lee Silvus

Thomas V Souvignier

William G Bliss

Andrei Vityaev

Patricia Ann Thaler

Richard Martin Born

Kent Douglas Anderson

John P Mead

Peter Igorevich Vasiliev

Cenk Argon

Maurice David Caldwell

Yingquan Wu

Robert W Warren, Jr

Nan-Hsiung Yeh

Ewe Chye Tan

Purmina Naganathan

A transmitting device may implement a checksum for integrity verification for a message page during an auto-negotiation period. The checksum may provide redundancy to ensure the integrity of the message page after transmission. The checksum may be calculated based on the message page and appended to the message page for transmission. A receiving device may receive the message page with the appended checksum and calculate a checksum locally using the received message page. The calculated and received checksum may be compared by the receiving device to verify the integrity of the message.

Message page integrity verification in automotive network auto-negotiation

A network device includes a communication interface and a transmitter coupled to the communication interface. The transmitter is configured to determine to start an auto-negotiation page with a link partner, and transmit, through the communication interface, a start delimiter for the auto-negotiation page. The transmitter transmits the start delimiter by transmitting a first pulse comprising a first encoding violation, followed by a second pulse comprising a second encoding violation. The transmitter may shorten the first pulse and the second pulse relative to a different pre-defined start delimiter to define spectral content for the first pulse and the second pulse that passes different first and second receiver filters in the link partner for different first and second communication standards.

Bandwidth control for differential manchester encoding auto-negotiation signaling

Super block error correction code (ECC) adaptable to communication systems including hard disk drives (HDDs) and other memory storage devices. A means is presented by which a number of blocks of information can be organized, with a degree of ECC provided thereto, and transmitted via a signal into a communication channel. In some instances, the communication channel is coupled to a storage media as in the context of an HDD, and information is written to and read from the storage media via this communication channel (e.g., 'read channel'). This means is particularly well suited to applications that provide large amounts of data via any one transmission (e.g., DVR/PVR (Digital/Personal Video Recorder)). A redundant block is generated using the information of each of a number of information blocks thereby provided extra ECC on a large portion of data, and that redundant block also undergoes ECC encoding.

Super block error correction code (ECC) adaptable to communication systems including hard disk drives (HDDs) and other memory storage devices

A scheme in which a first decoder provides first decoding of a signal read from a disk. A second decoder, coupled to an output of the first decoder, combines with the first decoder to provide iterative decoding to recover data stored on the disk when in an iterative mode of operation. However, when in a non-iterative mode of operation, the output of the first decoder is coupled to an error correction code module to apply error correction code (ECC) to the output of the first decoder to recover data stored on the disk by non-iterative decoding.

Use of ECC with iterative decoding for iterative and non-iterative decoding in a read channel for a disk drive

Timing recovery optimization using disk clock. A novel means is presented to perform and provide control of the sampling frequency of a signal that is read from a disk within a hard disk drive (HDD). Two separate, yet somewhat cooperating control loops are employed to provide feedback control of the sampling frequency of the signal that is read from disk. A timing recovery loop and a disk clock loop operate in conjunction with one another according to some desired manner (which can be predetermined or adaptive) to ensure that the sampling of the signal is performed to a very accurate degree. In one implementation, the timing recovery loop governs the sampling rate until the disk clock loop has locked, from which time either the disk clock loop govern the sampling or some combination of the signals provided from the two loops govern the sampling.

Timing recovery optimization using disk clock

An interleaver has an input multiplexer that receives a data sequence at an interleaver input and that separates the data sequence into multiple data sub-blocks. The interleaver has a linear feedback shift register that generates an input address sequence. The interleaver has adder circuits that generate output address sequences associated with each data sub-block. The interleaver has memory that stores the data sub-blocks at addresses controlled by the input address sequence. The memory reproduces each data sub-block in an interleaved sequence controlled by the associated output address sequence. The interleaver has an output multiplexer that assembles the interleaved sequences to provide an interleaver output.

Interleaver with linear feedback shift register

A method leverages knowledge of the actual or ideal bit sequence to improve the performance of any sequence detector. This improved performance results by constraining the sequence detector when the sequence detector has knowledge of known patterns within the sample sequence. Embodiments may control or limit the effects of ISI on a readback signal in order to allow higher storage within physical media such as that of a HDD. This method involves reading an analog waveform from the physical media. The phase of this analog waveform is determined and it is sampled at regular intervals using a timing recovery scheme. This sample sequence is equalized (filtered) and sent to a sequence detector which will compare the received sequence to all possible transmitted sequences, generating a path through a trellis that represents the estimated sequence. That trellis path may pass through known states at certain times. This knowledge makes it possible to remove some of the paths under consideration. Then the sample sequence may be compared to a reduced set of possible bit sequences to select a decoded bit sequence.

Method for improving sequence detection performance by removing excess paths

A communications channel is provided, which includes a receive path having an iterative decoder and an ECC decoder. The iterative decoder has a soft channel detector with a soft output. The ECC decoder is coupled to decode bits produced from soft information received from the soft output and operates on the bits in a bit order that is the same as that on the soft output.

Iterative detector with ECC in channel domain

A method or apparatus that can form and test a data block variant by flipping a selected potentially bad bit that is consecutive with 1 or 2 sequences of several potentially good bits of a received block. The variant correctability test is optionally repeated several times before receiving another data block, in the event of ECC failures, each repetition using a different block variant.

Soft-decision decoding using selective bit flipping

Low complexity pseudo-random interleaver

A sequence generator is configured to be re-initialized to a value selected derived from a candidate group that is derived from a predetermined value. If and when the re-initializing is performed, it is fully performed within about one clock cycle of setting the sequence generator to the predetermined value. The sequence generator is optionally initialized by a local processor to which it is operatively coupled, after which the processor receives one sequence value each cycle.

Selective sequence generation method and apparatus

A signal processing system includes a receiver for receiving an analog signal. The system also includes an analog-to-digital converter (ADC) coupled to the receiver. At each of a series of time intervals, the ADC outputs sequential digital codes. Each digital code corresponds to a sampled analog value of the received analog signal at each sample interval. The system further includes a memory in which the sequential digital codes may be stored, and a processing circuit for converting the digital codes into a series of binary data bits. The conversion may be performed in a different sequence than the sequence in which the digital codes are stored in the memory.

Decoupling of analog input and digital output

A method and apparatus for communicating data is provided. The data is encoded in accordance with a run length limited (RLL) code. A seed is appended to the RLL encoded data. The seed can be used to alter the error correction code (ECC) parity to meet an RLL constraint.

Reverse error correction coding with run length limited constraint

An apparatus and a method of aligning data bits serially received at a channel input. A number of data bits including a first data bit are stored in a buffer that has a first buffer bit and a buffer size greater than the number of data bits. The data bits in the buffer are shifted to improve alignment of the first data bit and the first buffer bit. The shifted data bits are tested for alignment. If the testing of the data bits indicates correct alignment, then the aligned data bits are transmitted from the buffer to a host for use. If the testing of the data bits indicates misalignment, then the data bits are passed to an error handling process.

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Boulder, CO, United States of America

Gregory Lee Silvus