Cisco Technology, Inc.

National Semiconductor Corporation

Gregory Lee DeJager

James P Rivers

Stewart Findlater

Scott A Emery

David H Yen

James R Hamstra

David C Brief

Robert Gregory Twiss

Erik R Swenson

Santanu Sinha

Gordon Mackay

Van Van Nguyen

Gopakumar Parameswaran

Bradley D Erickson

Robert D Hastings

John K Chen

The network switches and computer readable mediums of the present invention allocate port assignments based on load, that is, the amount of data being forwarded through each port in the group. The load balancing of the present invention is preferably dynamic, that is, packets from a given stream may be forwarded on different ports depending upon each port's current utilization. When a new port is selected to transmit a particular packet stream, it is done so that the packets cannot be forwarded out of order. This is preferably accomplished by ensuring passage of a period of time sufficient to allow all packets of a given stream to be forwarded by a port before a different port is allocated to transmit packets of the same stream. The invention may be used in a variety of different network environments and speeds, including 10Base-T, 100Base-T, and Gigabit Ethernet, and other network environments.

Port aggregation load balancing

Provided are methods, apparatuses and systems for balancing the load of data transmissions through a port aggregation. The methods and apparatuses of the present invention allocate port assignments based on load, that is, the amount of data being forwarded through each port in the group. The load balancing of the present invention is preferably dynamic, that is, packets from a given stream may be forwarded on different ports depending upon each port's current utilization. When a new port is selected to transmit a particular packet stream, it is done so that the packets cannot be forwarded out of order. This is preferably accomplished by ensuring passage of a period of time sufficient to allow all packets of a given stream to be forwarded by a port before a different port is allocated to transmit packets of the same stream. The invention may be used in a variety of different network environments and speeds, including 10Base-T, 100Base-T, and Gigabit Ethernet, and other network environments.

A repeater, useable for connecting switches in a data communication network, is provided in a distributed and/or modular fashion. The repeater includes a plurality of separate and distinct components or modules connected to or at least partially housed in, the various switches which the repeater modules couple. The distributed and/or modular repeater facilitates accommodating various switching or repeater needs as a network grows or contracts. A light pipe, preferably integral with a module case, conveys indicator lights to a position visible when viewing a switch front panel. A heat spreader unit receives and/or conveys heat and/or protects against undue EMI. A collision-handling state machine transmits modified collision fragments so as to avoid reduction in interpacket gaps, e.g. by downstream repeater modules.

Distributed network repeater module and method

A memory system reducing or eliminating the effects of DRAM page-opening delays or row access delays is provided. The system uses DRAM and fast memory such as SRAM. SRAM is used to store the initial portions of data from data blocks and corresponding portions of DRAM are used to store the terminal portions of data from the data blocks. When access to a block of data is requested, DRAM row access procedures are initiated. During the delay period, while DRAM row access procedures are occurring, the initial portion of data from the requested block is read-out from SRAM. By about the time the initial data read-out from SRAM is completed, DRAM row access procedures are completed and the remaining portion of the data is read-out from DRAM.

Method and apparatus for improving performance of DRAM subsystems with

A physical layer (PHY) device which can operate as a conventional PHY or as a repeater in a communication system. The PHY repeater supports four optional modes which may be enabled by programming control register bits with a microcontroller. These optional modes are: pass all symbols, enable noise filter, pass violation symbols and pass line states. When the pass all symbols, pass violation symbols and pass line states modes are enabled, the PHY device operates as a 'transparent' repeater. The repeater allows errors in a data stream to be encoded and repeated without filtering to a downstream station. The repeater also allows line states to be repeated without station management software. A single repeater may be used to couple two stations or multiple repeaters may be connected to form multi-port repeater boxes which can be connected to facilitate more reliable connections between stations.

Method and apparatus for repeating data

A physical layer (PHY) device which can operate as a conventional PHY or as an intelligent repeater in a communication system. The PHY device supports four optional modes which may be enabled by programming control register bits with a microcontroller. These optional modes are: pass all symbols, enable noise filter, pass violation symbols and pass line states. During operation as an intelligent repeater, the pass all symbols, pass violation symbols and pass line states modes are enabled. The intelligent repeater allows errors in a data stream to be encoded and repeated without filtering to a downstream station. The intelligent repeater also allows line states to be repeated without station management software. A single intelligent repeater may be used to couple two stations or multiple intelligent repeaters may be connected to form multi-port repeater boxes which can be connected to facilitate more reliable connections between stations.

Intelligent repeater functionality

An integrated circuit has an isochronous network port for receiving isochronous information from an isochronous network. To allow the integrated circuit to receive information packaged in accordance with two different packaging protocols (for example, HDLC and ATM), the integrated circuit includes a first framer/deframer circuit for deframing information packaged in accordance with a first packaging protocol (for example, HDLC) and a second framer/deframer circuit for deframing information packaged in accordance with a second packaging protocol (for example, ATM). A circuit switch is provided to cause incoming data to be deframed by the appropriate framer/deframer circuit depending on which slot of the network frame contained the information. Once deframed, a buffer manager controls storing of the information in a circular ring buffer in an external memory. A device residing on a host bus coupled to the integrated circuit may then read the information from the circular ring buffer via a parallel bus port of the integrated circuit. Information may also pass in the opposite direction from the parallel bus port, through a buffer memory port to the buffer memory, and from the buffer memory through the buffer memory port, through an appropriate framer/deframer circuit, through the isochronous network port, and onto the network.

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San Jose, CA, United States of America

Gregory Lee DeJager