University of Michigan

Advanced Micro Devices Corporation

Arm Limited

Gregory Kengho Chen

David Theodore Blaauw

Dennis Sylvester

Scott McLean Hanson

Stephen Victor Kosonocky

Stuart David Biles

Trevor N Mudge

David Alan Fick

Ronald George Dreslinski, Jr

Michael John Wieckowski

Mingoo Seok

Power supply variations and jitter are measured by monitoring the performance of a ring oscillator on a cycle-by-cycle basis. Performance is measured by counting the number of stages of the ring oscillator that are traversed during the clock cycle and mapping the number of stages traversed to a particular voltage level. Counters are used to count the number of ring oscillator revolutions and latches are used to latch the state of the ring oscillator at the end of the cycle. Based on the counters and latches, a monitor output is generated that may also incorporate an adjustment for a reset delay associated with initializing the ring oscillator and counters to a known state.

Power supply monitor

An improved voltage reference generator is provided. The voltage reference generator comprises: a first transistor having a gate electrode biased to place the first transistor in a weak inversion mode; and a second transistor connected in series with said first transistor and having a gate electrode biased to place the second transistor in a weak inversion mode, where the threshold voltage of the first transistor is smaller than the threshold voltage of the second transistor and the gate electrode of the second transistor is electrically coupled to a drain electrode of the second transistor and the source electrode of the first transistor to form an output for a reference voltage.

Reference voltage generator having a two transistor design

An integrated circuit memoryis provided with an array of memory cellsand power supply circuitry. Detected operating errors in malfunctioning memory cellsare identified using a built-in-self-test controller. The power supply circuitryis then configured to alter the voltage supply to the malfunctioning memory cellsin an attempt to correct their operation. The voltage supply of the row containing the malfunctioning memory cell and the column containing the malfunctioning memory cell may both be altered. The voltage alteration may be an increase or a decrease in voltage supply depending upon the nature of the malfunction detected.

Integrated circuit memory power supply

An apparatus for processing datais provided with a time-to-digital converterwhich serves to measure signal processing delay through one or more signal paths through a processing stage. This measured delay generates a delay value representing a plurality of instances of the signal processing delay which have been measured. Analysis is performed under software control to estimate a worst case signal processing delay through the processing stage based upon the delay values which have been generated. An adjustment of the operating parameters, such as supply voltage and clock frequency, of the apparatus is made to provide a timing margin through the processing stage sufficient to satisfy the worst case signal processing delay which has been estimated without an excessive margin.

Operating parameter control of an apparatus for processing data

A data processing apparatus is provided having a cache memory comprising a data storage array and a tag array and a cache controller coupled to the cache memory responsive to a cache access request from processing circuitry to perform cache look ups. The cache memory is arranged such that it has a first memory cell group configured to operate in a first voltage domain and a second memory cell group configured to operate in a second voltage domain that is different from the first voltage domain. A corresponding data processing method is also provided.

Cache memory system for a data processing apparatus

A memory cellwithin an integrated circuit memory is provided with an access controllercoupled to a first pass gateand a second pass gate. During a write access to the memory cellboth the first pass gateand the second pass gateare opened. During a read access, the first pass gateis opened and the second pass gateis closed. This asymmetry in the read and write operations permits an asymmetry in the gates forming the memory cellthereby permitting changes to increase both read robustness and write robustness. The asymmetry in the design parameters of different gates can take the form of varying the gate length, the gate width and the threshold voltage so as to vary the conductance of different gates to suit their individual role within the memory cellwhich is operating in the asymmetric manner provided by the separate word line signals driving read operations and write operations.

Growing community of inventors

Ann Arbor, MI, United States of America

Gregory Kengho Chen