General Electric Company

Gregory Keith Dudoff

Stephen Daley Arthur

Zachary Matthew Stum

Richard J Saia

Dale M Brown

Kevin Sean Matocha

Robert Dwayne Gossman

David Alan Lilienfeld

Stacey Joy Kennerly

Victor Mario Torres

William Gregg Hawkins

Roger Raymond Kovalec

The subject matter disclosed herein relates to metal-oxide-semiconductor (MOS) devices, such as silicon carbide (SiC) power devices (e.g., MOSFETs, IGBTs, etc.) In an embodiment, a semiconductor device includes a gate oxide layer disposed on top of a semiconductor layer. The semiconductor device also includes a gate electrode having a tapered sidewall. Further, the gate electrode includes a polysilicon layer disposed on top of the gate oxide layer and a metal silicide layer disposed on top of the polysilicon layer.

Tapered gate electrode for semiconductor devices

A method for sputtering an aluminum layer on a surface of a semiconductor device is presented. The method includes three sputtering steps for depositing the aluminum layer, where each sputtering step includes at least one sputtering parameter that is different from a corresponding sputtering parameter of another sputtering step. The surface of the semiconductor device includes a dielectric layer having a plurality of openings formed through the dielectric layer.

Sputtering system and method for forming a metal layer on a semiconductor device

The present invention provides a method of fabricating a metal oxide semiconductor field effect transistor. The method includes the steps of forming a source region on a silicon carbide layer and annealing the source region. A gate oxide layer is formed on the source region and the silicon carbide layer. The method further includes providing a gate electrode on the gate oxide layer and disposing a dielectric layer on the gate electrode and the gate oxide layer. The method further includes etching a portion of the dielectric layer and a portion of the gate oxide layer to form sidewalls on the gate electrode. A metal layer is disposed on the gate electrode, the sidewalls and the source region. The method further includes forming a gate contact and a source contact by subjecting the metal layer to a temperature of at least about 800&#xb0; C. The gate contact and the source contact comprise a metal silicide. The distance between the gate contact and the source contact is less than about 0.6 &#x3bc;m. A vertical SiC MOSFET is also provided.

SiC MOSFETs and self-aligned fabrication methods thereof

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Clifton Park, NY, United States of America

Gregory Keith Dudoff