Alcatel Network Systems, Inc.

Gregory J Longendyke

David W Kuddes

A circuit is shown for arbitrating between inputs to provide all request inputs with the opportunity to be polled in substantially less time than is the case with known prior art round robin arbiters. This is accomplished by phase delaying the input clock to produce a plurality of different phase clock signals such that multiple arbiter circuits can be polled within a single clock cycle if the first few arbiter circuits do not have a request waiting. With proper speed of operation of arbiter circuits, the phase delay can be of a short enough duration that all of the arbiter circuits can be polled in a single clock cycle. With slower speed arbiter circuits, the total polling time can exceed one clock cycle but still be less than the number of clock cycles of prior art round robin circuits which typically was the number of arbiter circuits times a single clock cycle time duration.

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Rowlett, TX, United States of America

Gregory J Longendyke