Harris Corporation

Intersil Corporation

Johnson and Johnson Vision Care, Inc.

Gregory J Fisher

Kantilal Bacrania

Chong I Chi

Mario Sanchez

Randall Braxton Pugh

Adam Toner

Michael D Church

John T Gasner

Akira Ito

Bruce J Tesch

Renyuan Huang

Glenn A Dejong

Donald Scott Langford

Choong-Sun Rhee

Jeffrey M Johnston

Shen Tu

Dave Kutchmarick

Programmable timer circuits are disclosed. One timer circuit may include a reference circuit configured to generate a bias current, a current controlled oscillator configured to receive the bias current c, and a frequency divider network configured to divide an output of the oscillator. The timer circuit may be capable of timing for 24 hour period, while using less than 5nA of quiescent current.

Extended period timer circuits for ophthalmic devices

A digital-to-analog converter (DAC) includes a plurality of current sources on a substrate operable in a predetermined sequence of use for generating an output current based upon a digital input, and a connection network for establishing the predetermined sequence of use for the current sources based upon the actual current values and to increase performance of the DAC. For example, the predetermined sequence of use can be set to reduce integral non-linearity error of the DAC. The connection network may be provided by a plurality of fusible links selectively connected to set the predetermined sequence of use. The current sources may include a first group of most significant bit (MSB) current sources for a predetermined number of MSBs. In addition, the plurality of current sources may include a second group of mid-most significant bit (mid MSBs) current sources for a predetermined number of mid MSBs. The plurality of current sources have actual values sortable from lowest to highest, and each actual current value will define an error value with both a magnitude and polarity relative to the desired value. One embodiment for sorting the order of use of the current sources is based upon the error values.

Digital-to-analog converter including current sources operable in a

An analog-to-digital converter (ADC) includes a plurality of capacitors formed on a semiconductor substrate and having actual capacitance values statistically related to desired capacitance values, and a gain stage comprising an amplifier and capacitors selected to provide a more accurate gain for the gain stage. A first at least one capacitor is connected between an input and an output of the amplifier defining a feedback capacitance, and a second at least one capacitor is connected between the input of the amplifier and an input of the at least one gain stage defining an input capacitance. In addition, the ADC includes a connection network selectively connecting the first at least one capacitor and the second at least one capacitor from among the plurality of capacitors to provide a desired ratio of feedback capacitance to input capacitance based upon the actual capacitance values. Accordingly, a gain can be set for the gain stage that is more accurate than would otherwise be obtained. The high accuracy switched capacitor gain stage may be used in other applications.

Analog-to-digital converter having enhanced accuracy gain stage, and

A digital-to-analog converter (DAC) includes a first array of current source cells extending in first and second transverse directions, and a two-dimensional symmetrical controller for operating current source cells of the first array based upon at least a portion of digital input words and in a symmetrical sequence in both the first and second directions with respect to a medial position of the first array. The medial position preferably defines a centroid for the first array. The two-dimensional symmetrical controller may preferably include a decoder for generating a plurality of control signals based upon predetermined most significant bits (MSBs) of digital input words. Another aspect of the invention relates to the treatment of the LSBs. According to this aspect, the first array further comprises a plurality of second current source cells, and the two-dimensional symmetrical controller further operates the plurality of second current source cells based upon predetermined LSBs of digital input words. The DAC may include a substantially identical second array adjacent the first array. The two-dimensional symmetrical controller may operate the current source cells in the first and second arrays in pairs and in a substantially mirror image sequence to provide geometrical averaging. The geometrical averaging may operate the current source cells in the first and second arrays in pairs and in a substantially true mirror or inverted mirror image sequence.

Digital-to-analog converter including current cell matrix with enhanced

The invention is a circuit and method for selecting a plurality of different types of resisters and for reliably manufacturing a current generator across different wafer lots. In one embodiment, a monolithic current generator applies the output voltage of a voltage reference circuit across a plurality of series-connected resisters of different types. The resisters are preferably statistically independent resisters, which permits a total resistance with a predefined standard resistance deviation across manufacturing wafer lots. An output current may then be produced which has a predefined standard current deviation across manufacturing wafer lots. In a preferred embodiment, no more than six different types of resisters are used. The resisters may be chosen from the group consisting of diffused resisters, implanted resisters, thin film resisters, metal resisters, and composite resisters. The present invention also includes a method for reliably producing current generators across wafer lots. A plurality of voltage reference circuits are formed in electrical connection with a plurality of n different types of series-connected resisters in a plurality of semiconductor die. Preferably, the plurality of n statistically independent resisters are formed with each resistor of the plurality of statistically independent resisters having a predefined standard resistance deviation across manufacturing wafer lots. An output voltage from respective ones of the voltage reference circuits applied across respective ones of the plurality of n different types of resisters would produce a plurality of respective output currents. Each of the respective output currents preferably has a predefined standard current deviation across manufacturing wafer lots.

Statistically based current generator circuit

Power monitoring circuit 5000 monitors a positive power supply Vcc and a negative power supply Vee. If either one or both power supplies fall below predetermined respective threshold values, a master reset pulse (MR) is generated. When both power supplies are at their normal operating level, the logic circuit 5040 generates a signal that enables operation of the circuit.

Integrated circuit with power monitor

The A-to-D converter 300 has an output buffer 320 with fourteen drivers each the same as driver 4100. Driver 4100 includes bipolar pull up pull down transistors 4102, 4103. Those transistors are both coupled to an output. Pull up transistor 4102 is coupled to a first reference voltage VDD; pull down transistor 4103 is coupled to a second or ground reference potential. A base drive circuit comprising a series connection between a resistor and a transistor 4121 to provide additional current to saturate the pull down transistor 4103 and thereby lower the collector-to-emitter voltage drop of transistor 4103 when transistor 4103 is turned on.

Analog-to-digital converter and output driver

An A-to-D converter 300 has a comparator 126 with a number of comparator cells 902. Each comparator cell 902 includes a current mirror 1700 that reduces kickback noise. Current mirror 1700 includes a bipolar current mirror 1705 and an NMOS current mirror 1709. The bipolar current mirror 1705 provides an ac ground paralleling NMOS transistor 1704 in the NMOS current mirror 1709 to reduce kickback noise.

Two stage current mirror

A comparator 10 has a first stage differential amplifier 11 coupled to a second stage, single ended differential amplifier 12. The output of the second stage is coupled to a latch input stage 15 of a latch 16. A latch replica bias circuit 20 operates the second stage at a clamp voltage corresponding to the threshold voltage of latch 16. A clock signal clk switches the second stage 12 between gain and clamp modes.

High speed comparator

A two-step analog-to-digital converter and BiCMOS fabrication method. The fabrication method provides pseudosubstrate isolation of digital CMOS devices from the analog devices. The converter uses NPN current switching in a flash analog-to-digital converter and in a digital-to-analog converter for low noise operation. CMOS digital error correction and BiCMOS output drivers provide high packing density plus large output load handling. Timing control aggregates switching events and puts them into intervals when noise sensitive operations are inactive. The fabrication method uses a thin epitaxial layer with limited thermal processing to provide NPN and PNP devices with large breakdown and Early voltages. Laser trimmed resistors provide small long term drift due to dopant stabilization in underlying BPSG and low hydrogen nitride passivation.

Analog-to-digital converter

Analog-to-digital converter and method of fabrication

A flash analog-digital (A/D) coverter for producing an n-bit binary number whose value is related to an analog input voltage value includes a resistor ladder network having 2.sup.n-1 +1 nodes. Each node is coupled to a comparator stage to provide an intermediate reference voltage to the stage. Each stage has a first output at which is provided a first output voltage whose value depends on whether the input voltage exceeds the intermediate reference voltage, and a second output voltage whose value depends on whether the input voltage exceeds the intermediate reference voltage by a least significant bit voltage. A combinational logic network is coupled to the first outputs of the stages for decoding the n-1 most significant bits of the n-bit number based on the highest intermediate reference voltage which does not exceed the input voltage. The network is further coupled to the second outputs of the stages to enable the second output of the stage corresponding to the highest intermediate voltage that does not exceed the input voltage through to be the least significant bit of the n-bit number.

Flash analog-to-digital converter employing least significant

A comparator having a differential sense amplifier connected to the output of an input comparator, and the decoding logic connected between the sense amplifier and the output latch. The comparator is designed for a flash A/D converter having a reference signal generator for one or more of the sense amplifiers.

Growing community of inventors

Indialantic, FL, United States of America

Gregory J Fisher