International Business Machines Corporation

Gregory J Cook

Cedric Lichtenau

Mary Prilotski Kusko

Timothy J Koprowski

Embodiments relate to design-based weighting for logic built-in self-test (LBIST). An aspect includes a computer program product for implementing design-based weighting for LBIST. The computer program product includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes analyzing, by the processing circuit, a plurality of integrated circuit design organizational units to determine preferred weightings of the integrated circuit design organizational units that provide a highest level of failure coverage when applied to a random pattern generator. Based on determining the preferred weightings, the processing circuit creates an integrated circuit layout that includes a plurality of weighted test paths to respectively apply the preferred weightings to the integrated circuit design organizational units. The integrated circuit layout is incorporated in a device under test.

Design-Based weighting for logic built-in self-test

Embodiments relate to design-based weighting for logic built-in self-test (LBIST). An aspect includes an integrated circuit development system for implementing design-based weighting for LBIST. The system includes a memory system to create an integrated circuit layout. A processing circuit is coupled to the memory system. The processing circuit is configured to execute integrated circuit development tools to perform a method. The method includes analyzing, by the processing circuit, a plurality of integrated circuit design organizational units to determine preferred weightings of the integrated circuit design organizational units that provide a highest level of failure coverage when applied to a random pattern generator. Based on determining the preferred weightings, the processing circuit creates an integrated circuit layout that includes a plurality of weighted test paths to respectively apply the preferred weightings to the integrated circuit design organizational units. The integrated circuit layout is incorporated in a device under test.

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Raleigh, NC, United States of America

Gregory J Cook