Microsoft Technology Licensing, LLC

Gregory Hogdal

John Eldridge

James A Stulz

Mark Sievert Larsen

Michael Chen

A technique to implement software debugging capability using breakpoints includes creating breakpoints, storing them in a watchlist, and paging out a virtual address (VA) to physical address (PA) page entry in a translation look-aside buffer (TLB). When software under test is run at full speed, memory is accessed via the TLB VA to PA page translations. When a translation is missing, an exception is generated. Handling the exception includes determining if the page missing from the TLB matches a breakpoint address in the watchlist. The address and operation type are compared to the watchlist. If the operation matches the address and not the specified data, then the software under test is single stepped, the TLB page is removed and the software under test continues to execute. If the breakpoint and data type matches, then a debugger is notified and debugger action to service the breakpoint occurs.

Fast data breakpoint emulation

Systems and methods are described for replicating virtual memory translation from a target computer on a host computer, and debugging a fault that occurred on the target computer on the host computer. The described techniques are utilized on a target computer having a processor that has halted execution. Virtual to physical address translation data from the target computer is transferred to the host computer. The host computer utilizes the virtual to physical address translation data to access data pointed by virtual memory addresses that were used by the target computer, and then debugs a fault by accessing the data by reading the physical memory addresson the host computer. After the virtual to physical memory address translation data have been acquired, they can be cached at the host computer.

Systems and methods for replicating virtual memory on a host computer and debugging using replicated memory

Systems and methods are described for replicating virtual memory translation from a target computer on a host computer, and debugging a fault that occurred on the target computer on the host computer. The described techniques are utilized on a target computer having a processor that has halted execution. Virtual to physical address translation data from the target computer is transferred to the host computer. The host computer utilizes the virtual to physical address translation data to access data pointed by virtual memory addresses that were used by the target computer, and then debugs a fault by accessing the data by reading the physical memory address on the host computer. After the virtual to physical memory address translation data have been acquired, they can be cached at the host computer.

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Gregory Hogdal