Broadcom Corporation

Cypress Semiconductor Corporation

Silicon Graphics, Incorporated

Gregory H Efland

Srinivasa H Garlapati

Jeff Z Guan

Jason A Trachewsky

Tom W Kwan

Somnath Paul

Haixiang Liang

Paul Anthony Lettieri

Venkat Kodavati

Gong-San Yu

Yuanjie Chen

Lin Yin

Gouri Pidugu

Timothy J Van Hook

Alan G Corry

Yongbing Wan

Kevin H Peterson

Larry C Yamano

Stephen C Fenwick

Ilya Stomakhin

Nino Pietro Ferrario

Meera Prahlad

George A Papanicolaou

Provided is a system and method for a modem including one or more processing paths. Also included is a number of interconnected modules sequentially arrayed along the one or more paths. Each module is configured to (i) process signals passed along the paths in accordance with the sequence and (ii) implement predetermined functions to perform the processing. Further, each of the modules has a particular degree of functional programmability and the degrees of functional programmability monotonically vary in accordance with the sequence.

Asymmetric digital subscriber line modem apparatus and methods therefor

Provided is a system and method for de-interleaving a data stream stored in a buffer having a plurality of memory locations. Each location has a memory width of (W) bytes and the data stream is formed of a number of data words each including (N) number of data bytes, and (N) is a non-integer multiple of the width (W). The method includes storing the data words into respective memory locations and appending each of the stored data words with number (X) of dummy bytes, a sum of (N)+(X) being an integer multiple of the width (W). The appended dummy bytes are then stored in the respective memory locations.

Method and system for copying DMA with separate strides by a modulo-n counter

An analog-to-digital converter (ADC) disposed in a data reception path to convert data from an analog format to a digital format is switched between two or more power modes to conserve power when data is not being received. ADC stays in a lower power-lower precision mode until an inbound data is detected, at which time the ADC switches to a higher power-higher precision mode to convert the data. Once data conversion is completed, the ADC switches back to the lower power-lower precision mode to conserve power.

Switching between lower and higher power modes in an ADC for lower/higher precision operations

Method and system for implementing a conditional one's complement of partial address

Method and system for synchronizing processor and DMA using ownership flags

Method and system for implementing SLICE instructions

A digital-to-analog converter (DAC) disposed in a data transmission path to convert data from a digital format to an analog format to be transmitted is powered down during a receive mode of operation for a wireless communication device. Likewise, an analog-to-digital converter (ADC) disposed in a data reception path to convert received data from an analog format to a digital format is powered down during a transmit mode of operation.

Powering down of DAC and ADC for receive/transmit modes of operation in a wireless device

A method and processor configured to handle an exception may employ a &ldquo;retry&rdquo; signal, which may be associated with a memory access attempt by the processor. The retry signal determines if an exception is to be serviced during a period in which the memory access is delayed. In one embodiment for which the exception is an interrupt, the retry signal is asserted when memory access is delayed and the processor may proceed to service an interrupt request during this period of delayed memory access, regardless of the degree of completion of an instruction by the processor. During a period of delayed memory access, the processor may suspend instruction execution until the memory access becomes available. Upon completion of servicing the interrupt, the processor may resume instruction execution beginning with the last instruction attempted before the suspension of the instruction execution due to the delayed memory access. In one embodiment, the processor may include interrupt handling logic to enable initiation of interrupt service in response to an interrupt request and may further include address selection logic to select an instruction address associated with a delayed memory access.

Low-latency interrupt handling during memory access delay periods in microprocessors

A method, system and processor are provided for minimizing latency and loss of processor bandwidth in a pipelined processor when responding to an interrupt. The method advantageously avoids emptying and refilling the processor's instruction pipeline in order to service an interrupt request. Instead, a short sequence of instructions comprising the interrupt response is inserted into the pipeline. Normal pipeline operation stalls while the inserted instructions execute, but since flow is not disrupted the loss in bandwidth is not as great as if the pipeline were flushed. Furthermore, direct insertion of the instructions into the pipeline avoids the need for the processor to save its context and branch to an interrupt service routine in memory; this results in much faster response in servicing the interrupt, thereby reducing latency. In the preferred embodiment, the method applies to a pipelined processor having a RISC (Reduced Instruction Set Computer) architecture, which receives interrupt requests from one or more DMA memory controllers. The instructions inserted into the pipeline compute block address information for a DMA transfer. A system and processor implementing the method are disclosed, based on an enhancement of a conventional RISC processor design, and making use of registers and other existing logic resources within the processor. It is shown that the enhanced processor can respond to DMA interrupts with shorter latency and a smaller reduction in processor bandwidth than if conventional interrupt handling were used.

Low-latency DMA handling in pipelined processors

A system and method for scaling image streams that use motion vectors is disclosed. The system combines an error term with a predicted term in order to produce a display value. The system operates on image components represented in the spatial and frequency domains. The system processes motion vectors in the spatial domain. The motion vectors are scaled. The integral part of the scaled motion vector addresses a framestore. The fractional portion of the scaled motion vector is input to a nonlinear filter which determines the value of image components for a location that does not correspond with an image location in the framestore. The output of the nonlinear filter comprises the predicted terms. Data in the frequency domain is processed more efficiently by reducing the size of a block of data by appropriate filtering. The resulting data is transformed to the spatial domain.

System and method for the scaling of image streams that use motion

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Palo Alto, CA, United States of America

Gregory H Efland