Intel Corporation

Bipolar Integrated Technology, Inc.

Gregory F Taylor

Tawfik Arabi

Chee How Lim

Chi-Yeu Chao

Keng L Wong

Hung-Piao Ma

Songmin Kim

James R Peterson

Shai Rotem

Mohamed A Abdelmoneum

Jeffrey E Smith

Zhanping Chen

George L Geannopoulos

David E Duarte

Gregory M Iovino

Avner Kornfeld

Payman Aminzadeh

Patrick Elwer

Dan Murray

Ravishankar Kuppuswamy

Ravisangar Muniandy

Jun He

Rachael Jade Parker

Edward Paul Osburn

Usman Mughal

Bob Elkind

Razi Uddin

Ananda G Sarangi

Jeffrey Hicks

Douglas R Parker

Srirama Pedarla

Jay D Lessert

Lawrence T Clark

Kevin X Zhang

Terrance J Dishongh

Larry E Mosley

Andrew W Yeoh

Jonathan P Douglas

Xia Dai

Kevin Fischer

Atul Maheshwari

Praveen Mosalikanti

Tawfik M Rahal-Arabi

Mark L Neidengard

David H Pullen

Timothy M Wilson

Kent R Callahan

Roshan J Fernando

Cangsang Zhao

Patrick John Ott

Srirama Pedaria

Thomas D Barrett

Paola Zepeda

Jack A Price

Golnaz Kaveh

Kevin J Fischer

Embodiments of the present disclosure provide self-calibrated thermal sensors of an integrated circuit (IC) die and associated techniques and configurations. In one embodiment, a self-calibrating thermal sensing device includes a resonator configured to oscillate at a frequency corresponding with a temperature of circuitry of an integrated circuit (IC) die, wherein the resonator is thermally coupled with the circuitry and configured to operate in a first mode and a second mode and logic operatively coupled with the resonator, and configured to calculate a first temperature corresponding with a first frequency of the resonator in the first mode using a first equation, calculate a second temperature corresponding with a second frequency of the resonator in the second mode using a second equation, and add an offset to the first equation and the second equation based on a result of a comparison of the first temperature and the second temperature. Other embodiments may be described and/or claimed.

Self-calibrated thermal sensors of an integrated circuit die

Methods and apparatuses for Micro-Electro-Mechanical Systems (MEMS) resonator to monitor temperature in an integrated circuit. Fabricating the resonator in an interconnect layer provides a way to implement thermal detection means which is tolerant of manufacturing process variations. Sensor readout and control circuits can be on silicon if desired, for example, a positive feedback amplifier to form an oscillator in conjunction with the resonator and a counter to count oscillator frequency.

Thermal sensor using a vibrating MEMS resonator of a chip interconnect layer

A program circuit generates first and second currents to program the fuse. The second current is higher than the first current. A control circuit controls generating the first and second currents in succession.

Fuse programming schemes for robust yield

In one embodiment, an analog-to-digital conversion in an integrated circuit is evaluated by an on-die testing circuit. For example, the on-die test circuitcan characterize one or both of the linearity and monotonicity of the digital-to-analog conversion. The value of a conversion output for a digital input code may be compared to the value of a prior conversion output of a prior step to provide digital difference values for each step of a sweep of digital input codes. Digital difference values may be compared to one or more predetermined limits to provide one or more pass/fail tests on-board the die. Other embodiments are described and claimed.

On-die digital-to-analog conversion testing

A plurality of fuse cells are arranged in an array. One or more fuse cells include a pair of fuse devices to output a pair of voltages, respectively, wherein the pair of fuse devices are redundantly programmed. A sense amplifier is coupled to the plurality of fuse cells to read the pair of voltage outputs from each of the plurality of fuse cells, respectively. A comparator circuit is coupled to the sense amplifier to compare the pair of voltage outputs for each of the plurality of fuse cells and to output the compared result.

Fuse cell array with redundancy features

Embodiments of the invention include a trio of reliability oscillators. In one embodiment, an on-chip frequency compensation circuit includes a selectively enabled reliability oscillator to generate a reference oscillating signal, a clocked reliability oscillator to generate an AC degraded oscillating signal, and a static reliability oscillator to generate a DC bias degraded oscillating signal. A compare circuit coupled to the reliability oscillators compares the oscillating signals and generates a frequency compensation signal if the comparison determines that there is frequency degradation greater than a predetermined threshold.

On-chip frequency degradation compensation

A method and apparatus for an integrated circuit having a offset reference circuit block to receive an external voltage reference and output an offset reference voltage are described herein.

On-die offset reference circuit block

Some embodiments of the invention include apparatus and systems having integrated circuits. Terminals or pins of the integrated circuits are configured to be driven to a state, to be floated for a time interval, and to be measured to determine the state of the terminals after the time interval. The measurement involves sampling the RC time constant of leakage current of the terminals. Other embodiments are described and claimed.

AC testing of leakage current in integrated circuits using RC time constant

Systems for testing a plurality of integrated circuits at a plurality of frequencies and voltages is disclosed. In one embodiment, a plurality of integrated circuits is tested at least once within a predetermined set of combinations of frequencies and voltages. If the integrated circuit fails testing within any combination of a frequency and voltage within the predetermined set, the integrated circuit is retested at a different predetermined set of combinations of frequencies and voltages. If the integrated circuit fails testing within any combination of a frequency and voltage within the different predetermined set, the integrated circuit is discarded.

Arrangements having IC voltage and thermal resistance designated on a per IC basis

A system is provided that includes a phase lock loop component to output a first signal based on a reference clock signal and a feedback clock signal. A clock distribution network may distribute a clock signal based on the first signal output from the phase lock loop component. Additionally, a delay lock loop component may deskew a signal and adjust the clock signal distributed by the clock distribution network.

Phase locked loop system capable of deskewing

Arrangements having integrated circuit (IC) voltage and thermal resistance designated on a per IC basis.

Testing arrangement to distribute integrated circuits

Growing community of inventors

Portland, OR, United States of America

Gregory F Taylor