Texas Instruments Corporation

Other

Gregory Eric Howard

Angelo Pinto

Leland Scott Swanson

Jeffrey A Babcock

Scott G Balster

Alfred Haeusler

Siva Prakash Gurrum

Scott Balster

Darvin R Edwards

Donald Charles Abbott

Mark William Morgan

Vikas I Gupta

Philipp Steinmann

Naveen Krishna Yanduru

Bernardo Gallegos

Rajiv Carl Dunne

Manu Joseph Prakuzhy

Phillipp Steinmann

Jeffrey Babcock

Swaminathan Sankaran

Bradley Allen Kramer

Yanli Fan

Danielle Griffith

Mukul Saran

Gary Paul Morrison

Srinivasan Venkatraman

Bharadvaj Bhamidipati

Kurt Peter Wachtler

Matthew David Romig

Wei-Yan Shih

Satyendra Singh Chauhan

Andy Quang Tran

Karlheinz Muth

Patrick Francis Thompson

Snehamay Sinha

Manfred Schiekofer

Paul Joseph Hundt

Amneh Mohammad Akour

Stephen N Kiel

Marie-Solange Anne Milleron

Alfred Hausler

Navin Kalidas

Leland Swnson

Ricardo A Romani

Kartheinz Muth

Souvik Mukherjee

Modesto Garcia

A system on a package (SOP) can include a galvanic isolator. The galvanic isolator can include an input stage configured to transmit an input RF signal in response to receiving an input modulated signal. The galvanic isolator can also include a resonant coupler electrically isolated from the input stage by a dielectric. The resonant coupler can be configured to filter the input RF signal and transmit an output RF signal in response to the input RF signal. The galvanic isolator can further include an output stage electrically isolated from the resonant coupler by the dielectric. The output stage can be configured to provide an output modulated signal in response to receiving the output RF signal.

Galvanic isolator

A system and method integrates signal filters in a multiband transceiver. A preferred embodiment comprises an amplifier with a first tunable capacitor coupled to a signal input and a tunable filter. The tunable filter comprises an input stage with a first pair of inductors arranged in a dipole configuration and a second tunable capacitor coupled in parallel to the first pair of inductors and an output stage inductively coupled to the input stage, the output stage includes a second pair of inductors also arranged in a dipole configuration and a third tunable capacitor coupled in parallel to the second pair of inductors. The inductors are realized using bond wire or any other high Q material. The first tunable capacitor, the second tunable capacitor, and the third tunable capacitor can be tuned using a master-slave tuning configuration to adjust the operating frequency of the amplifier and the tunable filter to enable frequency band compatibility with multiple communications protocols.

Integrated radio frequency filters for multiband transceivers

A packaged semiconductor device including a leadframe and a plurality of angularly shaped capacitors. The leadframe includes structures with surfaces and sidewalls. The angularly shaped capacitors are attached to surface portions of the leadframe structures. The angularly shaped capacitors have sidewalls coplanar with structure sidewalls. The angularly shaped capacitors includes a conductive material attached to the structure surface. The conductive material having pores covered by oxide and filled with conductive polymer. The angularly shaped capacitors topped by electrodes are made of a second metal.

Semiconductor package having etched foil capacitor integrated into leadframe

An apparatus is provided. The apparatus generally comprises a plurality of pairs of differential transmission lines. The plurality of pairs of differential transmission lines includes a set of pairs of differential transmission lines with each pair of differential transmission lines from the set of pairs of differential transmission lines including at least one twist to alternate current direction. Also, the plurality of differential transmission lines are arranged such that alternating current directions substantially eliminate cross-talk across the plurality of pairs of differential transmission lines.

Differential transmission line pairs using a coupling orthogonalization approach to reduce cross-talk

A packaged semiconductor device including a leadframe made of a first metal, the leadframe including structures with surfaces and sidewalls; capacitors attached to surface portions of the leadframe structures, the capacitors having sidewalls coplanar with structure sidewalls; the capacitors including a foil of conductive material attached to the structure surface, the conductive material having pores covered by oxide and filled with conductive polymer, the capacitors topped by electrodes made of a second metal.

A method for fabricating a packaged semiconductor device begins by placing a first mask on a foil of porous conductive material bonded on a strip of a first metal. The surface of the conductive material and the inside of the pores are oxidized. The first mask leaves areas unprotected. The pores of the unprotected areas are filled with a conductive polymeric compound. A layer of a second metal is deposited on the conductive polymeric compound in the unprotected areas. The first mask is removed to expose un-oxidized conductive material. The foil thickness of the un-oxidized conductive material is removed to expose the underlying first metal. This creates sidewalls of the foil and leaves un-removed the capacitor areas covered by the second metal. A second mask is placed on the strip, the second mask defines a plurality of leadframes having chip pads and leads, and protecting the capacitor areas. The portions of the first metal exposed by the second mask are removed. Sidewalls of the first metal are coplanar with the foil sidewalls. The second mask is removed.

A system is provided for use with circuit layout design data having a set of differential pairs and a set of bond wire pairs. A layout portion can receive the circuit layout design data. A crosstalk calculating portion can determine a first amount of crosstalk in a circuit corresponding to the circuit layout design data. A modifier can modify the circuit layout design data into modified circuit layout design data such that one of the set of differential pairs and the set of bond wire pairs includes a crossover. The crosstalk calculating portion can further determine a second amount of crosstalk in a circuit corresponding to the modified circuit layout design data. An optimizer can compare the first amount of crosstalk with the second amount of crosstalk to generate optimized circuit layout design data. A layout designer can output the optimized circuit layout design data.

System and method of crossover determination in differential pair and bondwire pairs to minimize crosstalk

A semiconductor chip () with bond pads () on a substrate () with rows and columns of regularly pitched metal contact pads (). A zone comprises a first pair () and a parallel second pair () of contact pads, and a single contact pad () for ground potential; staggered pairs of stitch pads () connected to respective pairs of adjacent contact pads by parallel and equal-length traces (, etc.). Parallel and equal-length bonding wires (, etc.) connect bond pad pairs to stitch pad pairs, forming differential pairs of parallel and equal-length conductor lines. Two differential pairs in parallel and symmetrical position form a transmitter/receiver cell for conducting high-frequency signals.

Structure for high-speed signal integrity in semiconductor package with single-metal-layer substrate

The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer () beneath the gate dielectric () and source and drain regions () of a MOS transistor. The carbon containing layer () will prevent the diffusion of dopants into the region () directly beneath the gate dielectric layer ().

Advanced CMOS using super steep retrograde wells

An apparatus is provided. The apparatus comprises a substrate and a circuit trace. The substrate includes a region that is adapted to receive a discrete component, a metal layer, a dielectric layer formed over the metal layer, a window formed in the metal layer that underlies the region, and a conductive strap that extends across the window. The circuit trace is formed on the dielectric layer and is discontinuous across the region.

Apparatus for broadband matching

An integrated circuit (IC) device includes an electromigration resistant feed line. The IC device includes a substrate including active circuitry. A back end of the line (BEOL) metallization stack includes an interconnect metal layer that is coupled to a bond pad by the EM resistant feed line. A bonding feature is on the bond pad. The feed line includes a uniform portion and patterned trace portion that extends to the bond pad which includes at least three sub-traces that are electrically in parallel. The sub-traces are sized so that a number of squares associated with each of the sub-traces are within a range of a mean number of squares for the sub-traces plus or minus twenty percent or a current density provided to the bonding feature through each sub-trace is within a range of a mean current density provided to the bonding feature plus or minus twenty percent.

IC device having electromigration resistant feed line structures

A hermetic MEMS device () comprising a carrier () having a surface () including a device () and an attachment stripe (), the stripe spaced from the device and surrounding the device; a metallic foil () having a central bulge portion () and a peripheral rim portion () meeting the stripe, the bulge cross section parallel to the carrier monotonically decreasing from the rim () towards the bulge apex (); and the foil positioned over the carrier surface so that the bulge arches over the device and the rim forms a seal with the stripe.

MEMS package having formed metal lid

An integrated circuit and method of fabricating the integrated circuit is disclosed. The integrated circuit includes vertical bipolar transistors (), each having a buried collector region ('). A carbon-bearing diffusion barrier () is disposed over the buried collector region (&#x2032;), to inhibit the diffusion of dopant from the buried collector region (&#x2032;) into the overlying epitaxial layer (). The diffusion barrier () may be formed by incorporating a carbon source into the epitaxial formation of the overlying layer (), or by ion implantation. In the case of ion implantation of carbon or SiGeC, masks () may be used to define the locations of the buried collector regions (&#x2032;) that are to receive the carbon; for example, portions underlying eventual collector contacts () may be masked from the carbon implant so that dopant from the buried collector region (&#x2032;) can diffuse upward to meet the contact (). MOS transistors () including the diffusion barrier () are also disclosed.

Control of dopant diffusion from buried layers in bipolar integrated circuits

Thermal communication of matched transistors formed in lower electrical resistance subregions of first and second active substrate regions is provided by thermally conductive members formed to extend over isolation regions between higher electrical resistance subregions of the first and second regions. In one form, thermal communication is done, with or without contacts, through insulating layers to metal layers formed over the substrate. In another form, thermal communication is done through a polysilicon layer formed over the substrate.

Thermally enhanced semiconductor devices

Growing community of inventors

Dallas, TX, United States of America

Gregory Eric Howard