Koninklijke Philips Corporation N.V.

Facebook Technologies, LLC

Meta Platforms Technologies, LLC

Nxp B.v.

Sonics, Incorporated

Gregory Ehmann

Drew Eric Wingard

Timothy A Pontius

Neal Thomas Wingen

David R Evoy

Jun Wang

D C Sessions

Neeraj Upasani

Wojciech Stefan Powiertowski

Shrirang Madhav Yardi

Miguel Angel Guerrero

Arjan Bink

Ennio Salemi

Marco Brambilla

George Spatz

Swati Saxena

Jeffrey Ryden

Minli Lin

Neil Gregie

The disclosure describes techniques for hierarchical power management of memory of an artificial reality system to reduce power consumption by the memory. An example device may be a peripheral device configured to generate artificial reality content for display or a head-mounted display unit (HMD) configured to output artificial reality content for display. The device includes memory divided into multiple memory blocks configurable to operate in a plurality of power modes. The device also includes memory block controllers controlling memory blocks. Each memory block controller controls which power mode in which the corresponding memory block is to operate, independent of any of the other memory blocks. The device includes a memory power controller configured to configure control registers of the memory block controllers to direct the memory block controllers to select one of the plurality of power modes for the memory blocks when the memory blocks are not being accessed.

Hierarchical power management of memory for artificial reality systems

The disclosure describes techniques for interrupt and inter-processor communication (IPC) mechanisms that are shared among computer processors. For example, an artificial reality system includes a plurality of processors and an inter-processor communication (IPC) unit. The IPC unit includes one or more doorbell registers, wherein each doorbell register is associated with a uniquely assigned source processor and a uniquely assigned target processor. Each doorbell register is further configured to store doorbell data indicative of whether an interrupt is a high priority interrupt or a low priority interrupt. The IPC unit may also include one or more FIFO (first-in first-out) memories configured to store data associated with each interrupt.

Artificial reality system with inter-processor communication (IPC)

The disclosure describes techniques for interrupt and inter-processor communication (IPC) mechanisms that are shared among computer processors. For example, an artificial reality system includes a plurality of processors; an inter-processor communication (IPC) unit comprising a register, wherein the IPC unit is configured to: receive a memory access request from a first processor of the processors, wherein the memory access request includes information indicative of a hardware identifier (HWID) associated with the first processor; determine whether the HWID associated with the first processor matches an HWID for the register of the IPC unit; and permit, based on determining that the HWID associated with the first processor matches the HWID for the register of the IPC unit, the memory access request to indicate a communication from the first processor to at least one other processor.

Methods, Apparatus, and Systems are discussed for a sequencer-based protocol adapter that executes a limited instruction set. The sequencer-based protocol adapter is implemented in electronic hardware and programmable registers in an integrated circuit and configured to transition a set of 1) one or more voltage sources, 2) one or more frequency sources, or 3) a combination of voltage sources and frequency sources, coupled with that sequencer-based protocol adapter. The sequencer-based protocol adapter manages power on the integrated circuit, via receiving a desired performance index at an input and then executing one or more of the limited instructions stored in the programmable registers in a proper sequence of steps in order to transition the coupled voltage sources and/or frequency sources from a current operational state to a desired operational state. Note, the desired operational state the coupled voltage sources and/or frequency sources corresponds to the received desired performance index.

Sequencer-based protocol adapter

In an embodiment, an operating point controller for two or more circuit regions in an integrated circuit is discussed. The OPC is configured to both i) set a resource state, including operating voltage and operating frequency, for each of those circuit regions, and ii) identify events to initiate transitions between two or more operating points for a given circuit region. The operating point controller is also configured to manage transitions between operating points for the two or more circuit regions on the integrated circuit. The operating point controller is a hardware based machine implemented in logic rather than software operating on a CPU processor.

Hardware-based operating point controller for circuit regions in an integrated circuit

In an embodiment, the OPC manages at least one of i) gating state and ii) different operating frequencies for a given circuit region. The operating point controller is configured to be capable of both 1) having sole control to set and manage the gating state and operating frequency for the given circuit region based on a first set of events, as well as 2) delegating control to a local power domain controller to set and manage i) gating state for components in that circuit region, ii) different operating frequencies for components in that circuit region, and iii) combinations of both, based on a second set of events, on a per operating point basis. The multiple operating points for that circuit region have different operating voltage levels and operating frequencies, and when delegated, the local power domain controller will chose the gating state and/or operating frequency.

Operating point controller for circuit regions

An arbitrator governs an arbitration between different power domains and sequences powering up the different power domains supplied by the same voltage supply (VS) circuit on the Chip. The arbitrator has sequencing logic that limits how many different power domains simultaneously power up to a maximum amount, which is less than enough instantaneous electrical current drawn on the VS-circuit to cause a reduction below a minimum allowable supply voltage level for the VS-circuit. The sequencing logic manages the sequencing of powering up the different power domains by factoring in i) whether different power domains arbitrating to power up are part of a set of power domains that share the VS-circuit, ii) an amount of an instantaneous electrical current drawn, and iii) an amount of credits available before the minimum allowable supply voltage level occurs for that VS-circuit. The sequencing logic controls a behavior of the power domains when powering up from multiple different behaviors.

Power manager with a power switch arbitrator

A testing approach involves selective application of clock signals to target circuitry. In an example embodiment (), a target circuit () having logic circuitry that processes data in response to an operational clock signal () having at least one clock period, is analyzed for delay faults. Test signals are applied to the logic circuitry while the logic circuitry is clocked with a high-speed test clock () having several clock-state transitions that occur during at least one clock period of the operational clock (). An output from the logic circuitry is analyzed for its state (e.g., as affected by delay in the circuitry). Delay faults are detected as a difference in state of the output of the logic circuitry. With this approach, circuits are tested using conventional testers () that operate at normal (e.g., slow) speeds while selectively clocking selected portions of the circuit at higher speeds for detecting speed-related faults therein.

Delay-fault testing method, related system and circuit

A high-speed parallel data communication approach overcomes data skewing concerns by concurrently transmitting data in a plurality of multiple-bit groups and, after receiving the concurrently-transmitted data, realigning skew-caused misalignments between the groups. In one particular example embodiment, for each group, an arrangement transfers the data in parallel and along with a clock signal for synchronizing digital data. The transferred digital data is synchronously collected via the clock signal for the group. At the receiving module, the data collected for each group is aligned using each group's dedicated clock signal. Skew across clock-domain groups is tolerated and overcome by processing the data and the skew first within each clock domain group, and then between groups.

Parallel data communication realignment of data sent in multiple groups

A circuit arrangement including a test-traffic generator, and adapted to communicate test-traffic onto a digital data path having other traffic sources. A first embodiment includes a data-generation circuit, a memory arrangement, state machine circuitry, and a status and feedback circuit. The memory arrangement stores a plurality of programmable commands indicative the type, pattern and behavior-in-time of the test-traffic. The data-generation circuit provides a data stream to the state machine circuitry, where the state machine assembles portions of the data stream into test-traffic having type, pattern and behavior-in-time characteristics selected responsive to the programmable commands. The state machine generates test-traffic on the digital data path. The status and feedback circuit monitors the digital data path for test-traffic, verifies the test-traffic against the data stream, and generates a feedback signal indicative of test-traffic quality or throughput. In another aspect of the present invention, a computer system includes a test-traffic generator.

Data communication bus traffic generator arrangement

An adaptive data communication approach permits communication bus monitoring by using a reconfigurable bus monitor built into the CPU bus structure and adapted to report back to the CPU in response to detecting certain CPU-programmed events. In one particular example embodiment, a circuit arrangement having a CPU circuit communicates with another device over a communication channel while a reconfigurable circuit monitors the communication channel. The CPU circuit configures the reconfigurable circuit for monitoring any of various types of event expected to occur on the communication channel. The reconfigurable circuit collects signals passed on the communication channel and reports back to the CPU circuit when data indicative of the first event type occurs on the communication channel. In response to the data indicative of the monitored event, the CPU circuit reconfigures the reconfigurable circuit to monitor for another event type occurring on the communication channel and thereby permits for an adaptive evaluation of the communication channel. Another aspect of the invention is directed to the CPU redirecting data communication in response to this adaptive evaluation.

System for bus monitoring using a reconfigurable bus monitor which is adapted to report back to CPU in response to detecting certain selected events

A high-speed parallel-data communication approach overcomes skewing problems by transferring digital data with automatic realignment. In one example embodiment, a parallel bus has parallel bus lines adapted to transfer digital data from a data file, along with a synchronizing clock signal. To calibrate the synchronization, the sending module transfers synchronization codes which are sampled and validated according to an edge of the clock signal by a receiving module and then used to time-adjust the edge of the clock signal relative to the synchronization codes. The synchronization codes are implemented to toggle the bus lines with each of the synchronization codes transferred.

Parallel data communication having multiple sync codes

In one example embodiment, a high-speed parallel-data communication approach transfers digital data in parallel from a first module to a second module over a communication channel including a plurality of parallel data-carrying lines and a clock path. The parallel bus lines are arranged in a plurality of groups, each of the groups including a plurality of data-carrying lines and a clock path adapted to carry a clock signal for synchronizing digital data carried from the first module to the second module. The sets of data are concurrently transferred using the groups of lines of the parallel bus, and at the second module and for each group, the transferred digital data is synchronously collected via the clock signal for the group. At the second module, the data collected for each group is aligned. By grouping the bus lines in groups with each group having its own clock domain, skew across clock-domain groups is tolerated and overcome by processing the data and the skew first within each clock domain group, and then between groups.

Parallel data communication having skew intolerant data groups

A first in, first out (FIFO) circular buffer enables high speed streaming data transfer between integrated circuit devices by performing more than one data element transfer unidirectionally by having a plurality of ports to address a memory array. In addition, the multiple transfers are performed during one bus cycle and the number of transfers may be selectable. FIFO control circuitry limits the number of data elements transferred in response to the state of the memory array including almost empty or almost full.

FIFO buffer that can read and/or write multiple and/or selectable number of data words per bus cycle

The operability and scaleability of electronic circuits is improved using a circuit arrangement that is modular, scaleable, straightforward to implement and allows for simple and safe physical design implementation. According to one example embodiment of the present invention, a reset method and system are used to effect a reset at several peripheral devices that may employ similar and/or different reset strategies. A reset module is coupled to a clock module having an external clock reference and to each of the peripheral devices. Operationally, the clock module provides a functional clock signal to each of the peripheral devices at one of a plurality of first frequencies. The reset module generates an internal reset signal in response to a system reset signal. In response to an internal reset signal, the clock module drives a common reset clock signal, having a reset clock frequency, to each of the peripheral devices via clock outputs at the clock module. The reset clock frequency is equal to or slower than the functional clock frequency provided to each of the peripheral devices. A synchronization module at each of the peripheral devices is adapted to synchronize the reset signal among all peripheral devices using the reset clock signal. The reset module holds the internal reset signal for a selected amount of time, and then releases the clock module from the reset clock signal. The resets are then simultaneously released at each of the peripheral devices, making possible a smooth transition from reset.

Growing community of inventors

Sleepy Hollow, IL, United States of America

Gregory Ehmann