Integrated Device Technology, Inc.

Cavium, Inc.

Nortel Networks Corporation

Gregory Edward Lund

Rajan Goyal

Gregg Alan Bouchard

Mohammad Shahanshah Akhter

Zixiong Wang

David Clifton Bond

Satyanarayana Lakshmipathi Billa

Thomas O Holtey

Victor Firoiu

Xiaohui Zhang

Eric Haversat

In one embodiment, a system includes a format block configured to receive a key, at least one rule, and rule formatting information. The rule can have one or more dimensions. The format block can be further configured to extract each of the dimensions from the at least one rule. The system can further include a plurality of dimension matching engines (DME). Each DME can be configured to receive the key and a corresponding formatted dimension, and process the key and the corresponding dimension for returning a match or nomatch. The system can further include a post processing block configured to analyze the matches or no matches returned from the DMEs and return a response based on the returned matches or nomatches.

System and method for rule matching in a processor

In one embodiment, a method includes encoding a key matching rule having at least one dimension by storing in a memory (i) a header of the key matching rule that has at least one header field, and (ii) at least one rule value field of the key matching rule corresponding to one of the dimensions.

Method and apparatus encoding a rule for a lookup request in a processor

A method and apparatus for a configurable packet routing, buffering and scheduling scheme to optimize throughput with deadlock prevention in SRIO-to-PCIe Bridges have been described. A single level enqueue method with dynamic buffering and dequeuing based on packet re-ordering is disclosed. Single level packet routing and scheduling to meet SRIO and PCIe rules to enqueue packets based on FType/TType is disclosed. Backpressure based on ingress watermarks for different packet types is disclosed. Use of a circular-reorder queue (CRQ) for both ingress and egress allows packet reordering and packet passing.

Method and apparatus for a configurable packet routing, buffering and scheduling scheme to optimize throughput with deadlock prevention in SRIO-to-PCIe bridges

A Balanced Packet Transmit Opportunity (BPTO) mechanism allows balanced bandwidth traffic to be serviced while still maintaining the service levels desired for high priority traffic. The above embodiment achieved the result by distinguishing both queue types and slot style types, and performing selections differently depending upon the relative styles of the queues and slots. This arrangement provides a number of advantages. Because the selection method is fast and relatively simple to implement, a large number of queues may be integrated into the decision process while maintaining a desired output bandwidth. In addition, the selection process provides a flexibility, allowing multiple traffic shaping considerations to be modified during operations to support changing network requirements. In addition, the selection process provides a flexibility, allowing multiple traffic shaping considerations to be modified during operations to support changing network requirements.

Queue scheduling with priority and weight sharing

Growing community of inventors

Eau Claire, WI, United States of America

Gregory Edward Lund