Micron Technology Incorporated

Gregory Edvenson

Jeremy Chritz

David Hulton

Corey B Olson

Paul T Draghicescu

Robert Trout

Apparatuses and methods are disclosed for an FPGA architecture that may improve processing speed and efficiency in processing less complex operands. Some applications may utilize operands that are less complex, such as operands that are 1, 2, or 4 bits, for example. In some examples, the DSP architecture may skip or avoid processing all received operands or may process a common operand more frequently than other operands. An example apparatus may include a first configurable logic unit configured to receive a first operand and a second operand; a second configurable logic unit configured to receive a third operand and the first calculated operand; a first switch configured to receive the first operand and a fourth operand and to output a first selected operand; and a second switch configured to receive the second calculated operand and the first selected operand.

DSP execution slice array to provide operands to multiple logic units

Apparatuses and methods are disclosed for an FPGA architecture that may improve processing speed and efficiency in processing less complex operands. Some applications may utilize operands that are less complex, such as operands that are 1, 2, or 4 bits, for example. In some examples, the DSP architecture may skip or avoid processing all received operands or may process a common operand more frequently than other operands. An example apparatus may include configurable logic blocks including DSP slices and an interconnected coupling the configurable logic blocks. An operand register of a DSP slice may include an operand input that is coupled to an output of that DSP slice.

DSP slice configured to forward operands to associated DSP slices

Representative embodiments are disclosed for a rapid and highly parallel configuration process for field programmable gate arrays (FPGAs). In a representative method embodiment, using a host processor, a first configuration bit image for an application is stored in a host memory; one of more FPGAs are configured with a communication functionality such as PCIe using a second configuration bit image stored in a nonvolatile memory; a message is transmitted by the host processor to the FPGAs, usually via PCIe lines, with the message comprising a memory address and also a file size of the first configuration bit image in the host memory; using a DMA engine, each FPGA obtains the first configuration bit image from the host memory and is then configured using the first configuration bit image. Primary FPGAs may further transmit the first configuration bit image to additional, secondary FPGAs, such as via JTAG lines, for their configuration.

High speed, parallel configuration of multiple field programmable gate arrays

Representative embodiments are disclosed for data transfer between field programmable gate arrays (FPGAs). A representative system includes: a PCIe communication network comprising a PCIe switch and a plurality of PCIe communication lines; a host computing system coupled to the PCIe communication network; a nonblocking crossbar switch; a plurality of memory circuits; and a plurality of field programmable gate arrays, each field programmable gate array configurable for a plurality of data transfers to and from the host computing system and any other field programmable gate array of the plurality of field programmable gate arrays, with each data transfer including a designation of a first memory address, a file size, and a stream number. Once base DMA registers have been initialized for a selected application, no further involvement by the host computing system is involved for the duration of the selected application.

System and method for independent, direct and parallel communication among multiple field programmable gate arrays

A system and method are disclosed for inexact search acceleration using reference data. A representative system includes one or more memory circuits storing a plurality of queries and a FM-index of the reference data; and one or more FPGAs configured to select a query; select a substring of the selected query; read a section of the FM-index and calculate a plurality of suffix array intervals for the sub string with a corresponding plurality of prepended characters in a first or next position; read a first or next character in the first or next position of the query and select a suffix array interval for the read first character; determine whether the suffix array interval is valid and whether a beginning of the query has been reached; returning a first search result when the suffix array interval is valid and the beginning of the query has been reached; and returning a second search result that no match of the query with the reference data was found when the suffix array interval is not valid.

Inexact search acceleration

A system and method are disclosed for inexact search acceleration using reference data. A representative system includes one or more memory circuits storing a plurality of queries and a FM-index of the reference data; and one or more FPGAs configured to select a query; select a substring of the selected query; read a section of the FM-index and calculate a plurality of suffix array intervals for the substring with a corresponding plurality of prepended characters in a first or next position; read a first or next character in the first or next position of the query and select a suffix array interval for the read first character; determine whether the suffix array interval is valid and whether a beginning of the query has been reached; returning a first search result when the suffix array interval is valid and the beginning of the query has been reached; and returning a second search result that no match of the query with the reference data was found when the suffix array interval is not valid.

Growing community of inventors

Seattle, WA, United States of America

Gregory Edvenson