Intel Corporation

Other

Gregory E Atwood

Albert Fazio

Kerry Dean Tedrow

James Q Mi

Jahanshir J Javanifard

Neal R Mielke

Johnny Javanifard

Stephen N Keeney

Jeffrey J Evertt

Jin-lien Lin

Krishna Kumar Parat

Paul D Ruby

Mark E Bauer

Daniel N Tang

Sanjay S Talreja

Owen W Jungroth

Glen N Wada

Kevin W Frary

James O Mi

Amit A Merchant

Been-Jon K Woo

James Brennan, Jr

Branislav Vajdic

Alan E Baker

Stefan K Lai

Tong-Chern Ong

Chin S Park

Marc E Landgraf

Kenneth E Wojciechowski

Lubin Y Gee

Richard A Lodenquai

Ho-Chun Liou

T C Ong

Kenneth Woiciechowski

The encapsulation of gate stacks of a semiconductor device in an oxide insulative layer and in a silicon nitride etch-stop layer allows the formation of a contact filling for connection to underlying diffusion regions without risk of accidental diffusion contact to gate shorts created by the contact filling. As a result, the gate stacks may be patterned closer together, thus reducing the cell size and increasing the cell density. Furthermore, use of the etch-stop layer makes contact lithography easier since the size of the contact opening can be increased and contact alignment tolerance made less stringent without concern of increasing the cell size or of creating diffusion contact to gate shorts.

Self-aligned contact process in semiconductor fabrication and device therefrom

A method and circuitry for programming a memory cell to one of at least three amounts of charge. The amount of charge placed in the memory cell is increased by increasing the voltage level of a programming pulse applied to the memory cell.

Method and circuitry for storing discrete amounts of charge in a single

Methods and apparatus for determining the state of a memory cell having more than two possible states are disclosed. For a first embodiment, the state of a flash cell having n states, where n is a power of 2, is determined by selectively comparing the threshold voltage V.sub.t of a selected memory cell to (n-1) reference voltages. For every two states, a single comparator is provided such that the total number of comparators is equal to the number of bits stored in the memory cell.

Sensing scheme for flash memory with multilevel cells

A variable stage charge pump for a flash memory device is described. The variable stage charge pump includes a first charge pump and a second charge pump. A first switch couples an output of the first charge pump to an input of the second charge pump. A second switch couples an input of the first charge pump to the input of the second charge pump. The first and second charge pump are series-coupled to a common output node when the first switch is in a first position and the second switch is in a second position, wherein the first and second charge pumps are parallel-coupled to the common output node when the first switch is in the second position and the second switch is in the first position.

Variable stage charge pump

A variable stage charge pump for a flash memory device is described. The variable stage charge pump includes a first charge pump and a second charge pump. A first switch couples an output of the first charge pump to an input of the second charge pump. A second switch couples an input of the first charge pump to the input of the second charge pump. The first and second charge pumps are series-coupled to a common output node when the first switch is in a first position and the second switch is in a second position, wherein the first and second charge pumps are parallel-coupled to the common output node when the first switch is in the second position and the second switch is in the first position.

A switching device having an electrically trimmable threshold voltage comprises a control transistor having favorable programming and erasing characteristics and a sensing transistor suited for stability and high drain voltages. The control transistor includes a floating gate for storing a charge. The control transistor receives an input voltage to vary the charge. The sensing transistor, which has a threshold voltage, includes the floating gate, which is formed from a single, contiguous layer of polysilicon or from separate polysilicon layers connected by metallization, such that the floating gate is shared by the control transistor and the sensing transistor. The control transistor has a tunnel oxide layer between a semiconductor layer and the floating gate having a thickness that is conducive to injection or tunneling of electrons through the tunnel oxide layer. The sensing transistor has a gate oxide layer between the semiconductor layer and the floating gate having a thickness greater than the thickness of the tunnel oxide layer, such as to substantially inhibit injection or tunneling of electrons through the gate oxide layer. Applying the input voltage to the control transistor varies the charge on the floating gate and thereby changes the threshold voltage of the sensing transistor.

Depletion and enhancement MOSFETs with electrically trimmable threshold

A method for programming an array of memory cells, wherein each memory cell has at least three possible states. The method comprises the steps of 1) analyzing a set of data to be programmed into the array of memory cells to determine destination states for each of the memory cells in the array, and 2) programming all memory cells to be programmed to a particular destination state, up to a maximum number of memory cells being programmed at any given time, until all memory cells having a particular destination state are programmed, whereupon all memory cells to be programmed to a next destination state are programmed in a like manner.

Programming flash memory using data stream analysis

Self-aligned contact process in semiconductor fabrication

A method for programming a memory cell having more than two possible states to a desired state. The method includes applying a programming pulse to the memory cell. The change in the amount of charge stored by the memory cell caused by applying the programming pulse to the memory cell is sensed. The control engine determines characterization information indicative of programming characteristics of the memory cell in response to the detected change in the amount of charge stored by the memory cell. The control engine then uses the characterization information to directly program the memory cell to approximately the desired state without performing a program verify operation.

Programming flash memory using predictive learning methods

In a memory device including an array of memory cells, each memory cell having more than two possible states, a method for programming a memory cell to a desired state. The method comprises a control engine programming a subset of the array of memory cells. Characterization information is determined from the step of programming the subset, wherein the characterization information indicates programming characteristics of a representative memory cell of the array of memory cells. The control engine then uses the characterization information to directly program the memory cell to approximately the desired state without performing a program verify operation.

Programming flash memory using distributed learning methods

A method for programming an array of memory cells wherein each cell may be placed in more than two states. The method comprises the steps of 1) selecting a plurality of different programming voltage levels wherein each programming voltage level is associated with a corresponding one of a plurality of states, and 2) applying a plurality of programming pulses to selected subsets of the array of memory cells, wherein each programming pulse has one of the programming voltage levels and one of a corresponding plurality of pulse widths such that each of the memory cells of a corresponding one of the selected subsets are programmed directly to a corresponding one of the plurality of states by a corresponding programming pulse.

Programming flash memory using strict ordering of states

Growing community of inventors

San Jose, CA, United States of America

Gregory E Atwood