Centre National De La Recherche Scientifique

Commissariat a L'energie Atomique Et Aux Energies Alternatives

Centre National De La Recherche Scientifique Universite Montpellier 2

Grégory Di Pendina

Edith Beigne

Guillaume Prenat

Eldar Zianbetov

Virgile Javerliac

Lionel Torres

Yoann Guillemenet

Rana Alhalabi

Jeremy Lopes

Kholdoun Torki

A memory comprising an array of memory cells, each memory cell comprising: first and second resistive storage elements each having at least first and second terminals; and a first transistor having: a first main conducting node connected to the first terminal of the first resistive element and to a first column/row line of the array; and a second main conducting node connected to the first terminal of the second resistive element and to a second column/row line of the array.

Compact magnetic storage memory cell

An asynchronous circuit which includes a first circuit suitable for receiving, from a first other circuit, a first data input signal, and for generating a first acknowledgement of receipt signal and a first data output signal; a second circuit suitable for receiving, from a second other circuit, a second data input signal, and for generating a second acknowledgement of receipt signal and a second data output signal, the second circuit being functionally equivalent to the first circuit; a comparator suitable for detecting an inconsistency between the first and second data input or output signals; and at least one circuit for pausing an acknowledgement of receipt suitable for preventing the propagation of the first and second acknowledgement of receipt signals towards the first and second other circuits if an inconsistency is detected by the comparator.

Radiation-resistant asynchronous communications

An asynchronous circuit including an asynchronous pipeline including two or more stages, each stage having: a buffering circuit for temporarily storing data to be transferred from one stage to the next based on a handshake protocol, the buffering circuit including a non-volatile memory; and a data presence detection circuit adapted to generate a data presence detection value indicating whether or not data is stored by the buffering circuit; and a control circuit adapted to perform a data back-up operation by independently controlling each buffering circuit to back-up the data it stores to its non-volatile memory based on the corresponding data presence detection value.

Data back-up in an asynchronous circuit

The invention concerns a memory cell comprising first and second resistive elements () coupled respectively between first and second storage nodes and first and second intermediate nodes, at least one of them being programmable to take up one of at least two resistive states (Rmax); a third transistor () coupled between the first and second intermediate nodes; a fourth transistor () coupled between the first storage node () and a data input node (); and a control circuit arranged, during a write phase, to activate the third and fourth transistors and to couple the data input node to a second supply voltage (VDD, GND) via a first circuit block () in order to generate a current in a first direction through the first and second resistive elements in order to program the resistive state of at least one of the elements.

Memory cell with non-volatile data storage

The invention concerns a memory cell comprising: first and second resistive elements (), at least one of which can be programmed to adopt at least two resistive states (RRmax); the first resistive element () being coupled between a first storage node () and a first intermediate node (), the second resistive element () being coupled between a second storage node () and a second intermediate node (); a transistor () coupled between the first and second intermediate nodes; and a control circuit arranged to activate the transistor while a second supply voltage (VDD, GND) is being applied to the first or second storage node to generate a programming current in a selected direction through the first and second resistive elements in order to program the resistive state of at least one of the elements.

Non-volatile memory cell

The invention concerns a circuit comprising: a C-element having first and second input nodes and first and second inverters () cross-coupled between first and second complementary storage nodes (, Z), the second storage node (Z) forming an output node of the C-element; and a non-volatile memory comprising: a first resistive element () having a first terminal coupled to the first storage node (); a second resistive element () having a first terminal coupled to the second storage node (Z), at least one of the first and second resistive elements being programmable to have one of at least two resistive states (R, R), wherein a second terminal of the first resistive element () is coupled to a second terminal of the second resistive element () via a first transistor (); and a control circuit ().

C-element with non-volatile back-up

The invention concerns a memory device comprising at least one memory cell comprising: a first transistor () coupled between a first storage node () and a first resistance switching element () programmed to have a first resistance; and a second transistor () coupled between a second storage node () and a second resistance switching element () programmed to have a second resistance, a control terminal of said first transistor being coupled to said second storage node, and a control terminal of said second transistor being coupled to said first storage node; and control circuitry () adapted to store a data value (D) at said first and second storage nodes by coupling said first and second storage nodes to a first supply voltage (V, GND), the data value being determined by the relative resistances of the first and second resistance switching elements.

Volatile/non-volatile memory cell

The invention concerns a memory device comprising: a first memory cell comprising a first resistive non-volatile data storage element programmable to store a first bit of data; and a second memory cell comprising a second resistive non-volatile data storage element programmable to store a second bit of data; wherein said first resistive element is configured to have a first data retention duration, and said second resistive element is configured to have a second data retention duration different from said first data retention duration.

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Echirolles, France

Grégory Di Pendina