Raytheon Company

Gregory D Tracy

Adam M Kennedy

Buu Quoc Diep

Stephen H Black

Thomas Allan Kocian

Tse E Wong

Thomas K Dougherty

John J Drab

Michael L Brest

Stephen A Gabelich

Kenneth L McAllister

Jeffrey P Yanevich

Janine F Lambe

Jay R Neumann

Thomas F McEwan

Tricia Veeder

David E Sigurdson

Alberto Perez

James E Scroggin

Julio C Dominguez

Kenneth L Mcallister

Thomas F Mcewan

A rigid-flex assembly (RFA) includes a circuit board attachable to a focal plane sensor. The RFA includes a flexible wiring section electrically coupled at opposing ends to the circuit board and to an edge connector. The flexible wiring section has a controlled separation distance or volume or vacuum gap between wiring strips for reduction of dielectric electrical loss and electrical cross talk. The flexible section has wires or traces configured to reduce the amount of copper used while optimizing signal integrity. Rigid substrates electrically couple the flexible wiring section to the connector. The RFA uses an end-launch, in-plane connection to the sensor for improved performance. A sensor module includes a housing and a sensor. An RFA is coupled to the sensor for high-speed data transfer and that optimizes signal integrity while providing thermal isolation via the flexible section.

Rigid-flex assembly for high-speed sensor module comprising a flexible wiring section with dual flexible strips stacked and attached together

A sealed package having a device disposed on a wafer structure and a lid structure boned to the device wafer. The device wafer includes: a substrate; a metal ring disposed on a surface portion of substrate around the device and a bonding material disposed on the metal ring. The metal ring extends laterally beyond at least one of an inner and outer edge of the bonding material. A first layer of the metal ring includes a stress relief buffer layer having a higher ductility than that of the surface portion of the substrate and a width greater than the width of the bonding material. The metal ring extends laterally beyond at least one of the inner and outer edges of the bonding material. The stress relief buffer layer has a coefficient of thermal expansion greater than the coefficient of expansion of the surface portion of the substrate and less than the coefficient of expansion of the bonding material.

Hermetically sealed package having stress reducing layer

A shutter assembly comprising a first planar member and a second planar member opposed from one another and forming a sleeve having a cavity therebetween, the sleeve having a pair of side rails adjacent the cavity along sides of the sleeve. A first shutter member having a first end is disposed in the cavity and slidingly disposed along one of the side rails, and a second shutter member having a second end is disposed in the cavity and slidingly disposed along the other side rail. The first end is opposed to the second end and is configured to be selectively advanced towards, and retracted from, the second end so as to define an aperture therebetween having a first shape when disposed in a first position, and wherein the aperture has a second larger shape when the first end is disposed in a second position. The first shutter member and the second shutter member maintain a thermal contact with the side rails and the planar members in all positions. The shutter assembly is well suited to be used at a cryogenic temperature and in a high vacuum environment.

Thermal control in variable aperture mechanism for cryogenic environment

An erase-on-demand memory cell() includes a memory layerand a heating layerthat can heat memory layerto at least an erase-effective temperature, to erase its data contents. Memory chips() and electronic systemsinclude cells(). Electronic systems() include logic circuitryto issue a signal to initiate heating. Electronic systems() include memory chips() with one or more erase-on-demand memory cells() that include a memory layer. One or more reservoirsstore chemicals. One or more valvesretain the chemicals, and respond to a signal to open, reacting the chemicals and/or exposing memory layersto the chemicals. A method of erasing data contents of memory cells includes determining existence of an erase demand scenario, generating a signal in response to the erase demand scenario, and actuating erasure of the memory cells upon issue of the signal.

Erase-on-demand memory cell

Growing community of inventors

Buellton, CA, United States of America

Gregory D Tracy