International Business Machines Corporation

Infineon Technologies Ag

Other

Gregory Costrini

Kia-Seng Low

Reinaldo Ariel Vega

Richard Stephan Wise

Ravikumar Ramachandran

David Michael Fried

John Patrick Hummel

Jeffrey P Gambino

Ramachandra Divakaruni

Frank Findeis

Kangguo Cheng

Ali Khakifirooz

Veeraraghavan S Basker

Chanro Park

Randy William Mann

Michael C Gaidis

Thomas L McDevitt

Byeong Yeol Kim

Xinhui Wang

John H Keller

Michael Vincent Aquilino

Ronald Dean Goldblatt

Walter Glashauser

John E Heidenreich, Iii

William L Nicoll

Igor Kasko

Hanfei Wang

Bruce Bennett Doris

Oleg Gluschenkov

Sivananda K Kanakasabapathy

Haizhou Yin

Katherine Lynn Saenger

Leland Chang

Christopher Vincent Jahnes

Eugene John O'Sullivan

Meikei Ieong

Gary Bela Bronner

Solomon Assefa

David Lee Rath

Wolfgang Raberg

David Edward Kotecki

Viraj Yashawant Sardesai

Jonathan Zanhong Sun

David M Dobuzinsky

Mahadevaiyer Krishnan

Panayotis Constantinou Andricacos

Thomas Safron Kanarsky

Christopher D Sheraw

Michael Joseph Rooks

Munir D Naeem

Chakrapani G Jambotkar

Mihel Seitz

Stephen L Brown

Gill Yong Lee

Peter D Hoh

Nakgeuon Seong

Joachim Nuetzel

Ihar Kasko

George Stojakovic

Wendy Yan

After forming a laterally contacting pair of a semiconductor fin and a conductive strap structure having a base portion vertically contacting a deep trench capacitor embedded in a substrate and a fin portion laterally contacting the semiconductor fin, conducting spikes that are formed on the sidewalls of the deep trench are removed or pushed deeper into the deep trench. Subsequently, a dielectric cap that inhibits epitaxial growth of a semiconductor material thereon is formed over at least a portion of the base portion of the conductive strap structure. The dielectric cap can be formed either over an entirety of the base portion having a stepped structure or on a distal portion of the base portion.

Structure and method to prevent EPI short between trenches in FinFET eDRAM

Semiconductor-oxide-containing gate dielectrics can be formed on surfaces of semiconductor fins prior to formation of a disposable gate structure. A high dielectric constant (high-k) dielectric spacer can be formed to protect each semiconductor-oxide-containing gate dielectric. Formation of the high-k dielectric spacers may be performed after formation of gate cavities by removal of disposable gate structures, or prior to formation of disposable gate structures. The high-k dielectric spacers can be used as protective layers during an anisotropic etch that vertically extends the gate cavity, and can be removed after vertical extension of the gate cavities. A subset of the semiconductor-oxide-containing gate dielectrics can be removed for formation of high-k gate dielectrics for first type devices, while another subset of the semiconductor-oxide-containing gate dielectrics can be employed as gate dielectrics for second type devices. The vertical extension of the gate cavities increases channel widths in the fin field effect transistors.

Protection of semiconductor-oxide-containing gate dielectric during replacement gate formation

Methods of forming an electrically conductive path under a barrier oxide layer of a semiconductor-on-insulator (SOI) substrate and an integrated circuit including the path are disclosed. In one embodiment, the method includes forming an electrically conductive path below a barrier oxide layer of a semiconductor-on-insulator (SOI) substrate, the method comprising: forming a first barrier oxide layer on a semiconductor substrate; forming the electrically conductive path within the first barrier oxide layer; and forming a second barrier oxide layer on the first barrier oxide layer. The electrically conductive path allows reduction of SRAM area by forming a wiring path underneath the barrier oxide layer on the SOI substrate.

Electrically conductive path forming below barrier oxide layer and integrated circuit

A method of forming a conductive spacer on a semiconductor device. The method includes depositing a polysilicon layer on the semiconductor device, selectively implanting dopant ions in the polysilicon layer on a first side of a transistor region of the semiconductor device to define a conductive spacer area, and removing the polysilicon layer except for the conductive spacer area. Optionally, a silicidation process can be performed on the conductive spacer area so that the conductive spacer is made up of metal silicide.

Conductive spacers for semiconductor devices and methods of forming

A pillar structure that is contacted by a vertical contact is formed in an integrated circuit. A hard mask is formed and utilized to pattern a least a portion of the pillar structure. The hard mask comprises carbon. Subsequently, the hard mask is removed. A conductive material is then deposited in a region previously occupied by the hard mask to form the vertical contact. The hard mask may, for example, comprise diamond-like carbon. The pillar structure may have a width or diameter less than about 100 nanometers.

Methods for fabricating contacts to pillar structures in integrated circuits

Disclosed are embodiments of a semiconductor structure with a partially self-aligned contact in lower portion of the contact is enlarged to reduce resistance without impacting device yield. Additionally, the structure optionally incorporates a thick middle-of-the-line (MOL) nitride stress film to enhance carrier mobility. Embodiments of the method of forming the structure comprise forming a sacrificial section in the intended location of the contact. This section is patterned so that it is self-aligned to the gate electrodes and only occupies space that is intended for the future contact. Dielectric layer(s) (e.g., an optional stress layer followed by an interlayer dielectric) may be deposited once the sacrificial section is in place. Conventional contact lithography is used to etch a contact hole through the dielectric layer(s) to the sacrificial section. The sacrificial section is then selectively removed to form a cavity and the contact is formed in the cavity and contact hole.

Method and structure for self-aligned device contacts

Disclosed are embodiments of a semiconductor structure with a partially selfaligned contact in lower portion of the contact is enlarged to reduce resistance without impacting device yield. Additionally, the structure optionally incorporates a thick middle-of-the-line (MOL) nitride stress film to enhance carrier mobility. Embodiments of the method of forming the structure comprise forming a sacrificial section in the intended location of the contact. This section is patterned so that it is self-aligned to the gate electrodes and only occupies space that is intended for the future contact. Dielectric layer(s) (e.g., an optional stress layer followed by an interlayer dielectric) may be deposited once the sacrificial section is in place. Conventional contact lithography is used to etch a contact hole through the dielectric layer(s) to the sacrificial section. The sacrificial section is then selectively removed to form a cavity and the contact is formed in the cavity and contact hole.

Disclosed are embodiments of a hybrid-orientation technology (HOT) wafer and a method of forming the HOT wafer with improved shallow trench isolation (STI) structures for patterning devices in both silicon-on-insulator (SOI) regions, having a first crystallographic orientation, and bulk regions, having a second crystallographic orientation. The improved STI structures are formed using a non-selective etch process to ensure that all of the STI structures and, particularly, the STI structures at the SOI-bulk interfaces, each extend to the semiconductor substrate and have an essentially homogeneous (i.e., single material) and planar (i.e., divot-free) bottom surface that is approximately parallel to the top surface of the substrate. Optionally, an additional selective etch process can be used to extend the STI structures a predetermined depth into the substrate.

Method for non-selective shallow trench isolation reactive ion etch for patterning hybrid-oriented devices compatible with high-performance highly-integrated logic devices

The present invention relates to a semiconductor device structure that includes at least one SRAM cell formed in a substrate. Such SRAM cell comprises two pull-up transistors, two pull-down transistors, and two pass-gate transistors. The pull-down transistors and the pass-gate transistors are substantially similar in channel widths and have substantially similar source-drain doping concentrations, while the SRAM cell has a beta ratio of at least 1.5. The substrate preferably comprises a hybrid substrate with at two isolated sets of regions, while carrier mobility in these two sets of regions differentiates by a factor of at least about 1.5. More preferably, the pull-down transistors of the SRAM cell are formed in one set of regions, and the pass-gate transistors are formed in the other set of regions, so that current flow in the pull-down transistors is larger than that in the pass-gate transistors.

Highly manufacturable SRAM cells in substrates with hybrid crystal orientation

Disclosed are embodiments of a semiconductor structure with a partially self-aligned contact in lower portion of the contact being enlarged to reduce resistance without impacting device yield. The semiconductor structure includes a substrate; at least two gate electrodes on the substrate; sidewall spacers adjacent to each of the gate electrodes; a silicide region on the substrate between the gate electrodes; and a contact on the silicide region, wherein the contact includes a self-aligned lower portion on the silicide region, which extends between the sidewall spacers and follows contours of the sidewall spacers, and an upper portion, and wherein the self-aligned lower portion includes a bottom surface adjacent to the silicide region and a top surface adjacent to the upper portion, with the upper portion being narrower than the top surface. Additionally, the structure optionally incorporates a thick middle-of-the-line (MOL) nitride stress film to enhance carrier mobility.

Semiconductor structure with self-aligned device contacts

Methods of patterning a magnetic stack of a magnetic memory cell and structures thereof. At least the top magnetic material layer of a magnetic stack is patterned using a hard mask, and a conformal insulating material is deposited over the patterned top magnetic material layer and hard mask. The conformal insulating material is anisotropically etched to remove the conformal insulating material over vertical sidewalls of at least the patterned top magnetic material layer and the hard mask. The remaining conformal insulating material comprises a sidewall spacer hard mask that is used as a mask to pattern the remaining material layers of the magnetic stack. The sidewall spacer hard mask may be left remaining in the magnetic memory cell structure.

Methods of patterning a magnetic stack of a magnetic memory cell and structures thereof

A method of forming a magnetic switching device is provided. The method includes depositing a bilayer hardmask, which may comprise a first mask layer of titanium nitride with a second mask layer of tungsten formed thereon. A first lithography process is performed to pattern the second mask layer, and a second lithography process is performed to pattern the first mask layer. Thereafter, the magnetic tunnel junction stack may be patterned in accordance with the first mask layer. An etching process may be performed to further pattern the first mask layer in accordance with the second mask layer. An optional passivation layer may be formed over the first mask layer and the second mask layer.

Magnetic switching device

Growing community of inventors

Hopewell Junction, NY, United States of America

Gregory Costrini