Texas Instruments Corporation

Gregory Charles Baldwin

Shashank Sureshchandra Ekbote

Youn Sung Choi

Younsung Choi

Oluwamuyiwa Oluwagbemiga Olubuyide

Thomas J Aton

Vikas I Gupta

Alwin J Tsao

David B Spratt

Timothy Alan Rost

E Ajith Amerasekera

James Walter Blatchford

Scott William Jessen

Robert L Pitts

Kayvan Sadra

Song Zhao

A method for increasing the performance of an integrated circuit by reducing the number of dummy gate geometries next to transistors in the speed path of an integrated circuit.

Dummy gate placement methodology to enhance integrated circuit performance

An integrated circuit containing core transistors and I/O transistors oriented perpendicular to the core transistors is formed by exposing a gate etch mask layer stack through a gate pattern photomask including core transistor gates and oversized I/O transistor gates. Core transistor gate lengths are defined by the gate pattern photomask. A first gate hardmask etch process removes the gate hardmask layer in exposed areas. The process continues with exposing a gate trim mask layer stack through a gate trim photomask. I/O gate lengths are defined by the gate trim photomask. A second gate hardmask etch process removes the gate hardmask layer in exposed areas. A gate etch operation removes polysilicon exposed by the gate hardmask layer to form gates for the core transistors and I/O transistors. The integrated circuit may also include I/O transistors oriented parallel to the core transistors, with gate lengths defined by the gate pattern photomask.

Methodology of forming CMOS gates on the secondary axis using double-patterning technique

An integrated circuit including one or more transistors in which source and drain regions are formed as embedded silicon-germanium (eSiGe). Guard ring structures in the integrated circuit are formed in single-crystal silicon, rather than in eSiGe. In one example, p-channel MOS transistors have source/drain regions formed in eSiGe, while the locations at which p-type guard rings are formed are masked from the recess etch and the eSiGe selective epitaxy. Defects caused by concentrated crystal strain at the corners of guard rings and similar structures are eliminated.

Device layout in integrated circuits to reduce stress from embedded silicon&#x2014;germanium

A method for forming an integrated circuit (IC) including a silicide block poly resistor (SIBLK poly resistor) includes forming a dielectric isolation region in a top semiconductor surface of a substrate. A polysilicon layer is formed including patterned resistor polysilicon on the dielectric isolation region and gate polysilicon on the top semiconductor surface. Implanting is performed using a first shared metal-oxide-semiconductor (MOS)/resistor polysilicon implant level for simultaneously implanting the patterned resistor polysilicon and gate polysilicon of a MOS transistor with at least a first dopant. Implanting is then performed using a second shared MOS/resistor polysilicon implant level for simultaneously implanting the patterned resistor polysilicon, gate polysilicon and source and drain regions of the MOS transistor with at least a second dopant. A metal silicide is formed on a first and second portion of a top surface of the patterned resistor polysilicon to form the SIBLK poly resistor.

Integrated circuit having silicide block resistor

An apparatus includes a plurality of die areas having integrated circuit (IC) die each having circuit elements for performing a circuit function, and scribe line areas between the die areas. At least one test module is formed in the scribe line areas. The test module includes a reference layout that includes at least one active reference MOS transistor that has a reference spacing value for each of a plurality of context dependent effect parameters, and a plurality of variant layouts. Each variant layout provides at least one active variant MOS transistor that provides a variation with respect to the reference spacing values for at least one of the plurality of context dependent effect parameters.

Scribe line test modules for in-line monitoring of context dependent effects for ICs including MOS devices

An integrated circuit (IC) die has an on-die parametric test module. A semiconductor substrate has die area, and a functional IC formed on an IC portion of the die area including a plurality of circuit elements configured for performing a circuit function. The on-die parametric test module is formed on the semiconductor substrate in a portion of the die area different from the IC portion. The on-die parametric test module includes a reference layout that provides at least one active reference MOS transistor, wherein the active reference MOS transistor has a reference spacing value for each of a plurality of context dependent effect parameters. A plurality of different variant layouts are included on the on-die parametric test module. Each variant layout provides at least one active variant MOS transistor that provides a variation with respect to the reference spacing value for at least one of the context dependent effect parameters.

On-die parametric test modules for in-line monitoring of context dependent effects

A mask build system includes a program for configuring mask layers and a fabrication site for compiling configured mask layers. The system includes at least one database configured by a system processor, the database comprising drawn layers for fabricating reticles of a semiconductor device; and a marker layer configured to define layer dependent features, the marker layer handed off with that part of the at least one database which will support subsequent layers of the database without altering flow of mask build at the fabrication site.

Marker layer to facilitate mask build with interactive layers

An integrated circuit constructed according to an arrangement of logic blocks, with one or more logic blocks including transistors of a different threshold voltage than in other logic blocks. Spacing between neighboring active regions of different threshold voltages is minimized by constraining the angle of implant for the threshold adjust implant, and by constraining the thickness of the mask layer used with that implant. These constraints ensure adequate implant of dopant into the channel region while blocking the implant into channel regions not subject to the threshold adjust, while avoiding shadowing from the mask layer. Efficiency is attained by constraining the direction of implant to substantially perpendicular to the run of the gate electrodes in the implanted regions.

Flexible integration of logic blocks with transistors of different threshold voltages

Various embodiments provide an integrated circuit (IC) design method and design kit for reducing context variations through design rule restrictions. The design method can be applied to components (e.g., analog blocks) with a context variation in an IC design. By drawing a cover layer over such components, context-variation-reduction design rule restrictions can be applied to reduce the context variations.

Method for minimizing transistor and analog component variation in CMOS processes through design rule restrictions

Device layout in integrated circuits to reduce stress from embedded silicon-germanium

In a split gate process for dual voltage chips, the N-type high-voltage transistors which are part of the ESD protection circuit, and therefore have the thicker gate oxide of the high-voltage transistors, can receive channel doping and drain extender doping which is the same as the core transistors. This causes these transistors to develop a high substrate current during an ESD event, triggering the protection circuit.

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Plano, TX, United States of America

Gregory Charles Baldwin