Barefoot Networks, Inc.

Pmc-sierra, Inc.

Gregory C Watson

Srivathsa Dhruvanarayan

Aled Justin Edwards

Glen Raymond Gibb

Constantine Calamvokis

Julianne Zhu

Steven Licking

Ravindra Sunkad

Sachin Bahadur

Balaji Satyanarayana Prabhakar

Nicholas W McKeown

Costas Calamvokis

Anders Swahn

Rolf Muralt

Shang-Tse Chuang

Steven Lin

Some embodiments provide a method for a parser of a processing pipeline. The method receives a packet for processing by a set of match-action stages of the processing pipeline. The method stores packet header field (PHF) values from a first set of PHFs of the packet in a set of data containers. The first set of PHFs are for use by the match-action stages. For a second set of PHFs not used by the match-action stages, the method generates descriptive data that identifies locations of the PHFs of the second set within the packet. The method sends (i) the set of data containers to the match-action stages and (ii) the packet data and the generated descriptive data outside of the match-action stages to a deparser that uses the packet data, generated descriptive data, and the set of data containers as modified by the match-action stages to reconstruct a modified packet.

Generation of descriptive data for packet fields

Some embodiments provide a method for a hardware forwarding element deparser. The method receives, from a match-action pipeline, (i) packet header field values stored in a set of data containers and (ii) a set of data indicating which packet header fields, of multiple possible packet header fields, to include in a packet constructed from the packet header field values. The method uses the received set of data and a list of data container identifiers for multiple possible packet header fields to generate an ordered list of references to data containers of the set of data containers. Based on the ordered list, the method constructs the packet using the packet header field values stored in the referenced data containers.

Configurable forwarding element deparser

A method of incremental updating of a network forwarding element that includes (i) a set of data plane circuits with a set of ingress buffers and a group of configurable packet processing stages and (ii) a set of control plane circuits comprising a set of direct memory access (DMA) buffers. Configuration data for reconfiguring the data plane packet processing stages is loaded into the DMA buffers while the packet processing stages are processing the packets. The ingress buffers are configured to (i) pause sending the packets to the processing stages and (ii) continue storing the incoming packets while sending the data plane packets to the processing stages is paused. The configuration data is loaded from the DMA buffers into the packet processing stages. The ingress buffers are configured to resume sending the data packet plane packets to the packet processing stages.

Incremental update of the data plane of a hardware forwarding element

Some embodiments provide a method for a deparser of a processing pipeline. The method receives, from a set of match-action stages of the pipeline, packet header field (PHF) values for a first set of PHFs of a packet processed by the match-action stages. The method also receives, directly from a parser of the pipeline, (i) packet data for the packet prior to any modification by the match-action stages and (ii) descriptive data that specifies locations within the packet data for a second set of PHFs of the packet that are not included in the first set of PHFs. The method constructs a packet from (i) the PHF values received for the first set of PHFs and (ii) the packet data received for the second set of PHFs. The descriptive data is used to extract packet header field values for the second set of PHFs from the packet data.

Packet reconstruction at deparser

Some embodiments of the invention provide a network forwarding element that includes a set of data plane circuits with several configurable packet processing stages for receiving and processing incoming packet traffic to the forwarding element. The forwarding element also includes a set of control plane circuits that include a set of direct memory access (DMA) buffers for configuring the configurable packet processing stages of the data plane. The control plane loads configuration data for reconfiguring the data plane packet processing stages into the set of DMA buffers while the data plane packet processing stages are processing the incoming packet traffic. The control plane pauses the incoming packet traffic to the data plane packet processing stages. The control plane loads the configuration data from the DMA buffers into the data plane packet processing stages. The control plane resumes the incoming packet traffic to the data plane packet processing stages.

Fast reconfiguration of the data plane of a hardware forwarding element

A packet-switch system utilizes a linecard-to-switch (LCS) protocol to integrate linecards with a switch core. Since the linecards include a majority of the buffering of the system and are located physically away from switch core, the size of the switch core can be reduced in size. The LCS protocol is a label-swapping, credit-based, flow-control, which enables the system to operate without requiring such information as the number of port modules available within a switch core or what Qualities of Service (QoS) or multicast flows are available. In addition, the LCS protocol enables the linecards to contain and manage the majority of the buffers in the system, and also to control the data drop policy within the system.

Packet-switch system

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Palo Alto, CA, United States of America

Gregory C Watson