Texas Instruments Corporation

International Business Machines Corporation

Gregory Boyd Shinn

Qi-Zhong Hong

Abbas Ali

Dhishan Kande

Thomas M Moore

Tae S Kim

Honglin Guo

Roger J Stierman

Benjamin James Timmer

Scott Robert Summerfelt

Mark R Visokay

Mahalingam Nandakumar

Bhaskar Srinivasan

Jeffrey Alan West

Jiong-Ping Lu

Girish Anant Dixit

Theodore Sidney Moise

Francis Gabriel Celii

Kelly Jay Taylor

Somnath S Nag

Ping Jiang

Kezhakkedath Ramunni Udayakumar

Sharad Saxena

Purnendu K Mozumder

Joe G Tran

Basab Chatterjee

Shawn T Walsh

Srini Raghavan

Wayne A Bather

Ju-Ai Ruan

Michelle L Hartsell

James B Friedmann

Troy A Yocum

Iqbal Ali

Jaideep Mavoori

Somit Joshi

Eric D Rullan

John E Campbell

Arun Sivasothy

Sudipto Ranendra Roy

Rajani C Shah

Shelley H Peterman

Joseph Jian Song

Michael J McGranaghan

Janice D Makos

An electronic device includes a semiconductor die having a multilevel metallization structure including stacked levels with respective dielectric layers and metal lines, and a low leakage, low hydrogen diffusion barrier layer on one of the stacked levels. The diffusion barrier layer contacts a side of the dielectric layer and the metal line of the one of the stacked levels, and the diffusion barrier layer includes silicon nitride material having a first bond percentage ratio of ammonia to silicon nitride that is greater than a second bond percentage ratio of silicon hydride to silicon nitride.

Dielectric silicon nitride barrier deposition process for improved metal leakage and adhesion

A device including a thin film resistor (TFR) structure. The TFR structure is accessible by one or more conductive vias that extend vertically from an upper metal layer to completely penetrate a TFR layer positioned thereunder. The conductive vias are coupled to one or more sidewalls of the TFR layer at or near the sites of penetration. The TFR structure can be manufactured by a method that includes etching a via trench completely through the TFR layer and a dielectric layer above the TFR layer, and filling the via trench with a conductor coupled to a sidewall of the TFR layer.

Thin film resistor with punch-through vias

An integrated circuit (IC) includes a substrate having a semiconductor surface layer with functional circuitry for realizing at least one circuit function, with an inter level dielectric (ILD) layer on a metal layer that is above the semiconductor surface layer. A thin film resistor (TFR) including a TFR layer is on the ILD layer. At least one vertical metal wall is on at least two sides of the TFR. The metal walls include at least 2 metal levels coupled by filled vias. The functional circuitry is outside the metal walls.

IC with thin film resistor with metal walls

In some embodiments, a method includes selecting, a first circuit layout, where the first circuit layout includes a circuit element representation, a design rule, and a target circuit element value. The method further includes receiving a plurality of circuit element values of circuit elements fabricated in each of multiple fabrication facilities using the design rule. The method also includes selecting a fabrication facility and a circuit element value of circuit elements fabricated in the selected fabrication facility using the design rule. Further the method includes determining a circuit element value calculation based on the selected circuit element values, and determining an adjustment value. This adjustment value is further used to customize the design rule. The method then includes generating a second circuit layout comprising the customized design rule, causing the fabrication facility to fabricate a circuit using the second circuit layout.

Customizing circuit layout design rules for fabrication facilities

A method of limiting plasma charging damage on ICs. A die includes gate stacks on active areas defined by a field dielectric. A pre-metal dielectric (PMD) layer is over the gate electrode. A contact masking material pattern is defined on the PMD layer including first contact defining features for forming active contacts and second contact defining features for forming dummy contacts (DC's) including over active areas and gate electrodes. Contacts are etched through the PMD layer using the contact masking material pattern to form active contacts and DC's. A patterned metal 1 (M1) layer is formed including first M1 portions over the active contacts and dummy M1 portions over the DC's. Metallization processing follows including forming interconnects so that the active contacts are connected to MOS transistors on the IC, and the DC's are not electrically connected to the MOS transistors.

Dummy contacts to mitigate plasma charging damage to gate dielectrics

An integrated circuit substrate containing an electrical probe pad structure over, and on both sides of, a dicing kerf lane. The electrical probe pad structure includes metal crack arresting strips adjacent to the dicing kerf lane. A metal density between the crack arresting strips is less than 70 percent. An electrical probe pad structure containing metal crack arresting strips, with a metal density between the crack arresting strips less than 70 percent. A process of forming an integrated circuit by forming an electrical probe pad structure over a dicing kerf lane adjacent to the integrated circuit, such that the electrical probe pad structure has metal crack arresting strips adjacent to the dicing kerf lane, and performing a dicing operation through the electrical probe pad structure.

Replacement of scribeline padframe with saw-friendly design

A method is provided for fabricating a ferroelectric capacitor structure including a method for etching and cleaning patterned ferroelectric capacitor structures in a semiconductor device. The method comprises etching portions of an upper electrode, etching ferroelectric material, and etching a lower electrode to define a patterned ferroelectric capacitor structure, and etching a portion of a lower electrode diffusion barrier structure. The method further comprises ashing the patterned ferroelectric capacitor structure using a first ashing process, where the ash comprises an oxygen/nitrogen/water-containing ash, performing a wet clean process after the first ashing process, and ashing the patterned ferroelectric capacitor structure using a second ashing process.

Method for leakage reduction in fabrication of high-density FRAM arrays

The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit including the semiconductor device. The method for manufacturing the semiconductor device, among other possible steps, includes forming a polysilicon gate electrode () over a substrate () and forming source/drain regions () in the substrate () proximate the polysilicon gate electrode (). The method further includes forming a protective layer () over the source/drain regions () and the polysilicon gate electrode (), then removing the protective layer () from over a top surface of the polysilicon gate electrode () while leaving the protective layer () over the source/drain regions (). After the protective layer () has been removed from over the top surface of the polysilicon gate electrode (), the polysilicon gate electrode () is silicided to form a silicided gate electrode (). The protective layer () is also removed from over the source/drain regions () and source/drain contact regions () are formed.

Integration scheme for using silicided dual work function metal gates

A method for reworking integrated circuit (IC) wafers having copper-metallized bond pads exposed in protective overcoat openings and one or more bondable metal layers deposited onto the bond pads by a technology which may produce some parts with off-spec or missing depositions. After identifying the wafer with off-spec metal layers, a layer of glass buffer is deposited over those wafers, which also fill any missing depositions at least partially. The glass-covered surface is then chemically-mechanically polished until the off-spec metal layers and at least portion a portion of the protective overcoat are removed, without damaging the copper metallization. Finally, a fresh layer of protective overcoat is deposited, selectively opened to expose the bond pads, and provided anew with one or more bondable metal layers.

Method for reworking metal layers on integrated circuit bond pads

A method for forming planar isolation structures for integrated circuits. A etch barrier is formed over the isolation fill material and an etch back is performed to remove material above unetched portions of the substrate. The exposed fill material is etched and planarized to form a planar isolation structure.

Shallow trench isolation planarization using self aligned isotropic etch

A method for reworking integrated circuit (IC) wafers having copper-metallized bond pads exposed in protective overcoat openings and one or more bondable metal layers deposited onto the bond pads by a technology which may produce some parts with off-spec or missing depositions. After identifying the wafer with off-spec metal layers, a layer of glass buffer is deposited over those wafers, which also fill any missing depositions at least partially. The glass-covered surface is then chemically-mechanically polished until the off-spec metal layers and at least a portion of the protective overcoat are removed, without damaging the copper metallization. Finally, a fresh layer of protective overcoat is deposited, selectively opened to expose the bond pads, and provided anew with one or more bondable metal layers.

A low-temperature pre-metal dielectric deposition process using phosphine-based chemistry in a high-density plasma chemical-vapor deposition technique. The process uses a phosphorous-doped oxide of up to 3.5 percent (wt) deposited at less than 350 degrees C. capable of filling 0.4 micron spaces between poly-silicon gates without microvoids.

Self-planarizing low-temperature doped-silicate-glass process capable of gap-filling narrow spaces

Growing community of inventors

Dallas, TX, United States of America

Gregory Boyd Shinn