Sperry Rand Corporation

Sperry Corporation

Gregory B Wiedenman

Phillip W Marsh

Kenneth S Morley

Jeffrey L Williams

James K White

Gary H Frederickson

A method and apparatus for performing high speed graphics fill is provided. Any closed line geometric shape or polygon that can be defined by pixel position is stored in memory. The memory pixel positions are stored in address locations corresponding to row and column positions. A first sequential examination of the data is made in reverse raster scan order to make a preliminary determination of the pixel positions inside the closed polygon. A second sequential examination of the data is made in forward or regular raster scan order and a final determination is made whether the pixel positions are inside the polygon and shall be filled. The final determination of pixel positions to be filled is stored shortly before the graphics fill operation is performed so that the fill operation is performed in raster scan time at high speed.

Method and apparatus for high speed graphics fill

A video display control circuit, for an intelligent terminal, includes a large cost efficient Random-Access Memory (RAM). A portion of the RAM memory is utilized as a high speed character generator instead of employing a dedicated Read Only Memory (ROM). Novel timing and memory control circuits are provided which permit characters to be generated witout any delay or change of real character timing. The characters in RAM may be modified or changed which is not possible with dedicated Read Only Memories.

Programmable video display character control circuit using multi-purpose

A buffer memory arrangement for use in conjunction with a controller and a plurality of peripheral units and/or subsystems of a data processing system. The arrangement includes a dynamic RAM buffer memory for receiving and storing information from the peripheral units or subsystems and for supplying stored information to such units, an address pointer memory for storing buffer memory addresses identifying locations in buffer memory from which information is to be read or into which information is to be stored, and an encoder responsive to a request signal from a peripheral unit or subsystem for supplying an identity signal to the address pointer memory, which signal identifies the requesting peripheral unit or subsystem and specifies location in the address pointer memory containing buffer memory addresses which are to be applied to the buffer memory. Upon designating the location in buffer memory from which information is to be read or into which information is to be stored, the identified peripheral unit or subsystem signals the buffer memory to indicate that information is to be read or written; then, if information is to be written into the buffer memory, such information is supplied by the peripheral unit, and if information is to be read from the buffer memory, the buffer memory supplies such information to the requesting unit or subsystem.

Buffer memory arrangement

In a throughput error detection system, a redundant logic unit is provided along with a required logic unit for simultaneous operation therewith. The required logic unit and redundant logic unit both produce output data which, it is desired, will be the same. The output data from the required logic unit is supplied to a data bus and the output data of the redundant logic unit is supplied to a parity check digit generator. From the data received from the redundant logic unit, the parity check digit generator generates a parity check digit which is applied to the data bus along wih the data from the required logic unit. A parity checking circuit receives the data and the parity check digit from the data bus and a calculation is made by the circuit to determine if parity is correct. If parity is not correct, the checking circuit produces an alarm signal to alert a user.

Error detection system

Peripheral devices of a microprocessor controlled system initiate service request signals which are sent to a system controller over a single dedicated request line. Such request signals are accepted by the system controller on a priority basis, with only one service request signal being honored at any given time. Once honored, the system controller addresses the peripheral device and accepts a vector request word therefrom. The vector request word is then used by the system controller to generate an index signal to select a microaddress of the microroutine to be used to service a peripheral device's request.

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Sandy, UT, United States of America

Gregory B Wiedenman