Unisys Corporation

Gregory B Wiedenman

Nathan A Eckel

Larry L Byers

Kelvin S Vartti

Paul A Laberge

Paul A LaBerge

Donald W Mackenthun

Ferris T Price, Deceased

Thomas T Kubista

David J Tanglin

Randy L DeGarmo

Joel B Artmann

Mary C Roskowiak

Raymond G Ryan

Donald E Harding

A multiprocessor system in which a defer phase response method is utilized that allows for a deferring agent to interrupt the normal flow of bus transactions once it gains control of system interface bus. The deferring agent is allowed to look ahead to determine if a continuous stream of defer phase cycles are pending transfer. If pending, the deferring agent will not release control of the bus until the pending defer phase cycles have been depleted. The look ahead feature allows expedited return of higher priority defer data, while minimizing bus dead cycles caused by interleaving defer phase cycles with normal bus traffic.

Method and apparatus for providing overlapping defer phase responses

A method and apparatus is presented allowing multiple data pointers or addresses to be transferred without acknowledgment to Memory Controller () and Memory Controller () of Data Controller (). Data is then transferred in response to the data pointers from BUFFER () and Buffer () and may be stalled during the transfer in favor of a second data transfer. Once the second data transfer finishes, the first data transfer may be completed.

Method and apparatus for stacked address, bus to memory data transfer

Bus address, function and system information in relation to bus requests are maintained in a centralized location (). Parallel access to the centralized data is facilitated through the use of pointers to the centralized location. Bus transaction operations needing access to the centralized data are simultaneously connected to the data through the use of the pointer control (), rather than requiring the data to be sequentially transmitted to the bus transaction operations as required.

Method and apparatus for multiple sequence access to single entry queue

A method and apparatus to facilitate a history trace of system bus activity in a Symmetric Multi-Processor (SMP) environment. A dynamic scan capability is provided to User () via Computer () that allows dynamic configuration of History Control Register (), thus providing a maskable history stack of system bus activity to be obtained from History Memory () for subsequent analysis.

Method and apparatus for recording and monitoring bus activity in a multi-processor environment

A data transfer system uses a data buffer and individual control of each storage location within the data buffer for improved control of data block transfers. The storage locations are assigned deallocate, active, or valid assignment bands to enable transfer control of the data blocks within the system. The deallocated storage locations are returned to an allocation pool for use as a future resource, where the active and valid assignment bands remain unavailable until deallocated. Error checking and depth control prohibit consecutive allocation or deallocation assignments as well as overflow.

Buffered transfer of data blocks between memory and processors independent of the order of allocation of locations in the buffer

Coded requests are received from Memory Port Interfaces (and) and stored into Outgoing Queue (). Coded requests are also received from Transaction Pipeline (), some of which may be linked requests. In response to each linked request stored in Outgoing Queue (), multiple bus requests are generated by Outgoing Queue () and assembled by Assembler () and placed onto Bus Interface ().

Method and apparatus for spawning multiple requests from a single entry of a queue

An error detection and recovery apparatus for monitoring, and recovering from, errors in a system having one or more logic units. An error detector detects errors in the logic units, and provides error signals in response. A first error processor receives selected error signals, and performs system recovery according to the particular error signals present. A second error processor receives other selected error signals, and performs error recovery of the logic unit only, without affecting the rest of the system. The second error processor performs error recovery through real-time execution of error recovery routines at the logic unit. A selector is provided to determine which of the error signals are provided to the first and second error processors. A memory stack having multiple memory locations is also provided to store bus information captured from a bus, which can be used by the second error processor in its error recovery.

Programmable error detect/mask utilizing bus history stack

A circuit employing two delayed bus clock signals and timer logic to minimize the dead bus time occurring between consecutive bus drivers and providing additional protection against multiple, simultaneous bus drivers for a communications bus in a computer system. Skewed enable and disable clock signals based on an original bus clock feed combinational logic to set a transceiver enable line when control of the bus is granted for bus transfers. Bus transfers remain enabled, through use of a feedback path, as long as a bus grant signal is active. When the last cycle of the bus transfer occurs, or a bus transfer error occurs, the transceiver enable line goes inactive, thereby allowing other components coupled to the bus to gain control. Test mode and bus transfer status lines provide further mechanisms for controlling bus transfer operation.

Bus grant overlap circuit

A power loss detection and recovery circuit for providing continued memory operations upon loss of a supply voltage. Multiple independent power domains, each of which provides an electrically isolated supply voltage, are used to provide power to redundant memory circuitry. A loss of voltage or a degenerative voltage within a power domain is detected, and circuitry residing on a different operational power domain provides recovery operations to allow continued memory activity within that operational power domain. The memories residing in an adjacent pair of power domains redundant, and are therefore written to and read from simultaneously, and circuitry within an operational power domain will prevent further reading of data from the memory residing in a failed power domain, and will also prevent further writing of data to the memory residing in the failed power domain upon recognition of a failed supply voltage within a power domain.

Multiple power domain power loss detection and interface disable

An apparatus for monitoring the performance of a computer system. A number of performance monitoring hardware elements may be placed throughout a computer system to simultaneously monitor the performance of a number of distinct components within the computer system. An advantage of the present invention over a software based approach is that the present invention allows any node within the computer system to be monitored. In addition, the present invention does not run on the systems CPU and therefore the performance monitoring function does not decrease system performance while operating. Finally, because the present invention does not run on the system's CPU, the results of the performance monitoring function may be more accurate than a software base approach.

Performance monitor for digital computer system

A computer architecture for providing enhanced reliability by coupling a plurality of commonly shared busses called streets with a plurality of smart switching elements called HUBs. The streets are bi-directional busses for transferring data between HUB elements. The HUB elements are capable of directing data across the street structures to the desired destination. The HUB elements have a built in priority scheme for allowing high priority data to be transferred before low priority data. The either increase or decrease the number of HUB elements and streets can be.

Architecture for smart control of bi-directional transfer of data

A fault tolerant multiple phase clock distribution system for providing synchronized clock signals to multiple circuit loads. Multiple electrically isolated power domains are powered by redundant AC and DC power sourcing circuits to ensure continued operation upon partial failure of the AC or DC power sourcing circuits. Multiple oscillators from the multiple power domains are synchronized to produce a group of simultaneously synchronized clock signals. Multiple synchronized clock signals from this group are then selected by selection circuitry and selection control circuitry, and are distributed to multiple circuit loads requiring simultaneous synchronization. The oscillator circuitry, synchronization circuitry, selection circuitry, and distribution circuitry is all provided in redundant form, so that the partial failure of any of the circuitry will not result in a system stop. Error recovery circuitry monitors for proper synchronization of the synchronized clock signals, and provides for automatic or manual error recovery upon detection of a synchronization error. A single phase synchronized clock signal is generated to minimize synchronization complexities, and circuitry exists at the circuit loads to generate multiple phase enable signals to emulate a multiple phase clock.

Fault tolerant clock distribution system

A skew fault detection system for detecting clock skew between two clock phases utilizes a plurality of skew fault detection circuits each of which employs two D-type flip-flops. The clock terminals of both of these flip-flops are connected to one of the clock phases, and one of the clock phases is coupled to a delay circuit on the D input terminal of one of the flip-flops. The delay circuit is adjustable to correspond to the clock pulse delay that is inherent in the circuit that is being monitored to control the maximum amount of clock skew that is allowable before this flip-flop will set. If the clock skew exceeds this allowable time, a skew fault occurs and the flip-flop will set. The circuit compares the initiation of one clock phase against the initiation of the other clock phase and to determine when the initiation of one clock phase occurs earlier than the initiation of the other clock pulse by a time duration that exceeds a predetermined allowable skew amount of time. Majority voting circuits may be employed to allow for detection failure of more than one skew fault detection circuit.

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Woodbury, MN, United States of America

Gregory B Wiedenman