Intel Corporation

Gregory B Tucker

Vinodh Gopal

James D Guilford

Lawrence T Clark

Michael W Morrow

Jay S Heeb

Yuan-Po Ypt Tseng

Ali Minaei

Wajdi K Feghali

Sanjeev N Trika

Daniel Cutter

Piotr Wysocki

Minda Zhang

Jonathan M Hughes

Jackson Ellis

Brian R Mears

An embodiment of an electronic storage system includes one or more storage drives, at least one or more of the storage drives supporting erasure coding (EC); and a controller including logic to control local access to the one or more storage drives. The controller, in response to a write command, is to for one or more storage drives, allocate an intermediate buffer in the storage drive's non-volatile memory (NVM) to store intermediate data. The controller is to issue commands to a first storage drive to read old data, compute the intermediate data of the first storage drive as XOR of the old data and new data received in the write command, and atomically write the intermediate data of the first storage drive to the intermediate buffer of the first storage drive and write the new data to the first storage drive's NVM. The controller is to read the intermediate data of the first storage drive from the intermediate buffer of the first storage drive. The controller is further to issue commands to one or more EC storage drives to read the old data, compute result data as the old data XOR a galois field coefficient of the one or more EC storage drives multiplied by the intermediate data, and atomically write the old data to the intermediate buffer of the one or more EC storage drives and write the result data to the one or more EC storage drive's NVM. Other embodiments are disclosed and claimed.

Erasure coding write hole closure for solid-state drive (SSD) erasure coding

Technologies for computing rolling hashes include a computing device having a first hash table that includes a first plurality of random-valued entries and a second hash table that includes a second plurality of random-valued entries. The computing device retrieves a block of data from a data buffer and generates a hash based on the block of data, a previously generated hash, the first hash table, and the second hash table. The computing device further determines whether the generated hash matches a predefined trigger and records a data boundary in response to a determination that the generated hash matches the trigger.

Technologies for computing rolling hashes

Methods and apparatus are described by which data is compressed using semi-dynamic Huffman code generation. Embodiments generate symbol statistics over a portion of data. The symbol statistics are expanded to include all possible literals that could appear within the data. Any literal or reference added to the statistics may be given a frequency of one. The statistics are used to generate a semi-dynamic Huffman code. The entire data is then compressed using the semi-dynamic Huffman code.

Semi-dynamic, low latency compression

Briefly, in accordance with one embodiment of the invention, an integrated circuit has a voltage regulator and a clock divider that may be used to adjust the operational frequency and/or voltage potential of the integrated circuit to reduce the power consumption of the integrated circuit while in operation.

Apparatus having adjustable operational modes and method therefore

An execution unit that performs both Reed-Solomon Error Correction Code (R-S ECC) encoding and R-S ECC syndrome generation within a combinational circuit coupled between an input buffer and an output buffer.

Integrated reed-solomon error correction code encoder and syndrome generator

Growing community of inventors

Chandler, AZ, United States of America

Gregory B Tucker