Maxim Integrated Products, Inc.

Lsi Logic Corporation

Pmc-sierra Us, Inc.

Microsemi Solutions (us), Inc.

Gregory Arthur Tabor

John Matthew Adams

Kurt Schwemmer

Michael B Anderson

Armando Garza Benavidez

Phillip Wayne Roberts

Larrie Simon Carr

Mark J Jander

Richard David Sodke

Kuan Hua Tan

Steven K Skoog

Keith Graham Shaw

Kevin James Witt

Kiran Hanchinal

Salman Ghufran

Methods, devices, and systems relating to Serial Attached SCSI (SAS) storage interconnect technology are provided. An SAS serial connection is established between an SAS initiator and an SAS expander over a physical link for communications between the SAS initiator and a plurality of target devices. The plurality of target devices is in communication with the SAS expander. SAS packets associated with each of the plurality of target devices are dynamically multiplexed and transmitted over the single SAS serial connection. Each SAS packet comprises one or more information bits indicating the target device with which the SAS packet is associated. The dynamically multiplexed SAS packets transmitted over the SAS connection may comprise SAS packets associated with at least two target devices having different maximum physical link rates. A result may be improved bandwidth utilization of the physical link when legacy SAS target devices with slower physical link rates are utilized.

Fractional multiplexing of serial attached small computer system interface links

An apparatus and method for port mirroring in a plurality of Peripheral Component Interconnect express (PCIe) interfaces includes, for each PCIe interface, output transmission ports for transmitting data to a central processing unit (CPU), receiving input ports for receiving data from the CPU, port-mirror-in (PM_IN) ports, and port-mirror-out (PM_OUT) ports provided in a PHY layer instance. The PM_OUT ports of each PHY layer instance is coupled to the PM_IN ports of a next PHY layer instance such that the PHY layer instances of the plurality of PCIe interfaces are connected in a ring bus architecture for mirroring one or more ports of the output transmission ports or the receiving input ports of a first active PHY layer instance can be mirrored to output transmission ports of a second PHY layer instance.

Port mirroring for peripheral component interconnect express devices

A SAS expander includes a switch core, a number of SAS expander phys coupled to the switch core, an SMP originator coupled to the switch core and an SMP receptor coupled to the switch core. In an embodiment, the SMP originator is configured to only send connection requests and the SMP receptor is configured to only receive connection requests. Program instructions stored in non-transient digital storage media include code segments detecting a new connection request, code segments determining whether the new connection request is in conflict with an existing connection request and code segments determining if there is a free destination receptor phy. In an embodiment, the free destination receptor phy is never operationally used for an origination of a connection request.

SAS expander with non-blocking virtual phy architecture

Provided is an apparatus and method for enabling interoperability between a serial attached small computer system interface (SAS) protocol with a peripheral component interconnect express (PCIe) protocol. A SAS-PCIe bridge includes a SAS component configured to communicate with a SAS device in a SAS domain and a PCIe component configured to communicate with a PCIe switch in a PCIe domain. The SAS component and the PCIe component are configured to convert data between the SAS protocol and the PCIe protocol.

Apparatus and method for interoperability between SAS and PCI express

A SAS expander including a switch core and a plurality of SAS expander phys coupled to the switch core, where at least two of the SAS expander phys are SAS expander multimode phys. In an embodiment, the SAS expander multimode phys include at least a normal operational mode and an alternate operational mode. In another embodiment, the SAS expander multimode phys also include a second alternate operational mode.

SAS expander with multimode phys

Various embodiments of the invention provide resource management of available data bandwidth of a SAS system in a non-uniform way. In certain embodiments, arbitration wait time values are adaptively modified to achieve a specified performance quota for a link.

Dynamic resource allocation for serial attached SCSI devices

Various embodiments of the innovation provide adaptive equalization training for a receiver in a communication system. In certain embodiments, the receiver's coefficients are re-optimized while links are active and initialized.

Non-disruptive adapter equalizer coefficient update method for active links

SAS expander with non-blocking virtual PHY architecture

The invention relates to the transmission of telemetry data from a stylus to a host computer via a serial, asynchronous data channel. The telemetry data is encoded into code-words using a specially selected error detecting or error correcting code, the code-words are transmitted from the stylus in a continuous, homogeneous data stream without the use of framing delimiters between adjacent code-words, and the code-words are then received by the host computer which separates the code-words according to the unique characteristics of the selected code. The code may be chosen based on both the error detection/correction requirements of the system and the probability that the code will create invalid intermediate code matches between consecutive back-to-back code-words. In one embodiment, the invention provides a synchronization scheme which greatly reduces the probability that invalid intermediate code matches will be recognized in the host computer as validly transmitted code-words.

Telemetry encoding technique for smart stylus

A precise timing delay method and apparatus. A phase-locked loop (PLL) in combination with a timing reference is used to calibrate a precise delay. These delays are then duplicated throughout the chip and controlled by the same current as in the PLL. This makes the delays process, voltage, and temperature insensitive. The delays can be programmed by selecting the desired delay through a multiplexer. Providing high precision delays are particularly advantageous for use in devices such as computer bus isolators.

Method and apparatus for providing precise circuit delays

A fully digital clock multiplier capable of generating any N/M multiple of an input clock frequency with a precise duty cycle is provided. The input clock signal is divided by M to create a divided clock signal. The propagation of the input clock signal along a delay cell string during a half cycle of the divided clock signal is then measured. The measured propagation is then scaled by a factor N to select an appropriate delay cell string length within a ring oscillator for generating an output signal.

Growing community of inventors

Colorado Springs, CO, United States of America

Gregory Arthur Tabor