Broadcom Corporation

Seagate Technology Incorporated

Archive Corporation

International Business Machines Corporation

Hewlett-packard Company

Quantum Corporation

Certance LLC

Gregory Alyn Unruh

William A Buchan

Jones V Howell

Yinyi Lin

Leroy J Thompson

Glen Alan Jaquette

Paul Frederick Bartlett

A frequency synthesizer includes circuitry configured to generate two or more feedback clocks based on the oscillation signals output from a voltage-controlled oscillator. The circuitry also modulates the feedback clocks based on fractional offsets from a reference clock frequency for input into two or more phase and frequency detectors. Multiple charge pump circuits receive inputs from these phase and frequency detectors. The current from these charge pumps is summed and input to a low pass filter. The output of the filter represents an average of the time difference between the reference clock and the multiple feedback clocks.

Apparatus and method for combining multiple charge pumps in phase locked loops

Various systems and methods utilizing a digitally controlled oscillator having frequency steps that increase in magnitude as a target output clock frequency increases are described. An integrated circuit in accordance with the disclosure includes a plurality of first transistor units fixedly coupled to an input voltage and a plurality of second transistor units switchably coupled to the first transistor units. An output coupled to the plurality of second transistor units and the plurality of first transistor units conveys an output signal having a frequency dependent on which select ones of the second transistor units are enabled. The plurality of second transistor units include a first switchable transistor unit having a transistor of a first width, a second switchable transistor unit having a transistor of a second width greater than the first width, and a third switchable transistor unit having a transistor of a third width greater than the second width.

Method and apparatus for control of a digital phase locked loop (DPLL) with exponentially shaped digitally controlled oscillator (DCO)

Data error detection comprises storing in a first buffer data to be written to a medium and a first digital signature of the data. If the first digital signature matches a second digital signature of data read from the first buffer, a compressed form of data read from the first buffer is stored in a FIFO. If the first digital signature matches a third digital signature of an uncompressed form of the compressed data, the uncompressed form of the compressed data, a C2 ECC of a first C1 ECC of the uncompressed form of the compressed data, and one or more C1 ECCs comprising the first C1 ECC and a second C1 ECC of the C2 ECC are stored in a second buffer. Success is indicated if the one or more C1 ECCs match corresponding C1 ECCs calculated from data and C1 ECCs read from the second buffer, and if a C1 ECC of the data read from the second buffer and written to a medium matches a C1 ECC of corresponding data read back from the medium.

Data error detection during media write

A cartridge handling system and method initialize a data storage cartridge having rewritable media and a cartridge memory for tamper resistant write once recording. A write-once flag is written to a lockable section of the cartridge memory also having a cartridge memory serial number, and the section locked to read-only. A write-once flag and the serial number are written to a required data set of the rewritable media, both thereby appearing in both locations of the cartridge.

Tamper resistant write once recording of a data storage cartridge having rewritable media

A data detection circuit for a read channel that recovers data encoded as the presence or absence of flux transitions on a magnetic recording medium, compares a current data sample of a read signal with a previous data sample and a threshold to determine whether the previous data sample represents a flux transition. The use of two data samples in the determination of flux transitions provides a more accurate detection of the data than comparing a single data sample to a threshold value. The data detection circuit generates an output data signal having data values based on the determined flux transitions of the data samples.

Method for detecting data encoded as state transitions in a read signal

Method and an arrangement for detecting state transitions in a read

A write equalization circuit that includes a data encoder for producing a binary data signal wherein a 1 is represented by a transition at the start of a bit interval and a 0 is represented by no transition at the start of a bit interval, and a nominal pulse generating circuit for producing nominal equalization pulses respectively synchronized with predetermined 0's in the binary signal. Adjusting circuitry responsive to the binary data signal and the nominal equalization pulses produces a write data signal that includes equalization pulses having a width and location in bit intervals that remain substantially constant with changes in component delays due to changing temperature and voltage, wherein the constant width and location of the equalization pulses are selected to achieve a predetermined suppression characteristic.

Adjustable write equalization for tape drives

A write equalization circuit that includes a data encoder for producing a binary data signal wherein a 1 is represented by a transition at the start of a bit interval and a 0 is represented by no transition at the start of a bit interval, an equalization timing generator for generating a start signal indicative of the initial edges of equalization pulses for predetermined 0's in the binary data signal, and a multiple stage delay delay circuit having logic gates implemented in an integrated circuit and responsive to the start signal and a control word for providing equalization pulses of a substantially constant width, wherein the number of stages employed for delay is determined by the control word. Logic circuitry implemented in the same integrated circuit as the multiple stage delay circuit detects changes in the propagation delay characteristics of the logic gates of the multiple stage delay circuit, and a processor responsive to the logic circuitry adjusts the control word so as to maintain the width of the equalization pulses substantially constant. Also disclosed is a method for adjusting write equalization pulses in a tape drive to achieve a desired suppression in the read signal.

Growing community of inventors

San Clemente, CA, United States of America

Gregory Alyn Unruh