Texas Instruments Corporation

Cirrus Logic Inc.

Luminary Micro, Inc.

Gregory Allen North

Per Torstein Roine

Eric Thierry Jean Peeters

Michael Zwerg

Murli Ganeshan

Brian Christopher Kircher

Scott Robert Summerfelt

Steven Craig Bartling

Sudhanshu Khanna

Douglas D Gephardt

Thomas Saroshan David

Wei-Yan Shih

Eric Thierry Peeters

James David Barnette

Scott Thomas Haban

Juergen Luebbe

Sudhakar Surendran

Maneesh Soni

Venkatraman Ramakrishnan

Robin Osa Hoel

Rajeev Suvarna

James Dub Austin

Atul Ramakant Lele

Dirk Preikszat

Tarjei Aaberge

Brian Kircher

Nikunj Khare

Ashwini Gopinath

Thomas A Fedorko

Thomas Hegedus

Leah Trautmann

Scott H R McMahon

Matthew Richard Perry

Embodiments disclosed herein relate to the management of a multi-trim oscillator to provide synchronization across multiple frequencies derived from the multi-trim oscillator without causing spurious pulses of clock output. In one example, a system provides a first clock signal via an oscillator and a second clock signal based on the first clock signal and a divider. The system further receives a first signal that indicates a change in a frequency of the first clock signal from a first frequency to a second frequency. In response to the first signal, the system determines an edge of the second clock signal and provides, at a time based on the edge of the second clock signal, a second signal to the oscillator to cause the change to the second frequency.

Dynamic control of a multi-trim oscillator

A system includes a multiplexer, an input/output (I/O) pin, a logic circuit, and a control register. The multiplexer has multiple inputs, an output, and a selection input. The logic circuit is coupled between the multiplexer and the I/O pin. The logic circuit has a first input. The control register includes first and second bit fields corresponding to the I/O pin. The first bit field is coupled to the selection input of the multiplexer, and the second bit field is coupled to the first input of the logic circuit.

Hardware-based security authentication

Aspects of the disclosure provide for an apparatus. In an example, the apparatus includes a clock switching circuit coupled to oscillators and one or more circuit units. The clock switching circuit is configured to receive, from the oscillators, a set of frequency signals, provide an uplink primary clock signal and an enable signal to the one or more circuit units, the enable signal determined synchronously with the uplink primary clock signal, receive, from the one or more circuit units or a clock management circuit, a clock frequency request, provide the uplink primary clock signal based on a first signal of the set of frequency signals, and according to the clock frequency request, determining whether to continue to provide the uplink primary clock signal based on the first signal or on a second signal of the set of frequency signals.

FSM based clock switching of asynchronous clocks

Various examples disclosed herein relate to trimming of system elements to prepare the elements for execution of boot code and application code. In an example embodiment, a system is provided. The system includes system control circuitry, direct memory access (DMA) circuitry, and processing circuitry. The system control circuitry is configured to instruct the DMA circuitry to obtain trim data from memory upon detecting that a first group of system elements has reached an initialized state. The DMA circuitry obtains the trim data and writes it to trim registers. The system control circuitry supplies the trim data to a second group of system elements to bring them to an operational level, then instructs the processing circuitry to execute boot code.

Device trimming via direct memory access

A system includes a multiplexer, an input/output (I/O) pin, a logic circuit, and a control register. The multiplexer has multiple inputs, an output, and a selection input. The logic circuit is coupled between the multiplexer and the I/O pin. The logic circuit hays a first input. The control register includes first and second bit fields corresponding to the I/O pin. The first bit field is coupled to the selection input of the multiplexer, and the second bit field is coupled to the first input of the logic circuit.

A piezoelectric sensor with: (i) a capacitive element, comprising piezoelectric material; (ii) a pre-conditioning circuit, comprising circuitry for establishing a polarization of the capacitive element in a polarizing mode; and (iii) signal amplification circuitry for providing a piezoelectric-responsive output signal, in response to charge across the capacitive element in a sensing mode.

Piezoelectric sensing apparatus and method

An embedded processor with a cryptographic co-processor operating in a multithreading environment, with inter-thread security for cryptography operations. A secure memory block accessible by the co-processor stores a plurality of key entries, each key entry storing data corresponding to a cryptography key, and a thread owner field that identifies an execution thread is associated with that key. A central processing unit issues a call to the co-processor to execute a cryptography operation along with a key identifier for the key to be used, and a thread identifier indicating the current execution thread. The co-processor compares the thread identifier received from the CPU with the thread owner field of the key entry corresponding to the key identifier. If the thread identifier matches the thread owner in the key entry, the key is retrieved from the secure memory block for use by the co-processor for the cryptography operation.

Thread ownership of keys for hardware-accelerated cryptography

Disclosed examples include interface circuits to transfer data between a first register in a fast clock domain and a second register in a slow clock domain, including a resettable synchronizer to provide a synchronized start signal synchronized to a slow clock signal to initiate a write from the first register to the second register according to a write request signal, a pulse generator circuit to provide a write enable pulse signal according to the synchronized start signal, a write control circuit to selectively connect an output of the first register to an input of the second register to write data from the first register to the second register according to the write enable pulse signal, and a dual flip-flop to provide a reset signal synchronized to a fast clock signal according to the write request signal to clear any prior pending write request and begin a new write operation.

Integrated circuits, methods and interface circuitry to synchronize data transfer between high and low speed clock domains

This invention is a method to extend data retention for FLASH based storage in a real time device embodied in generic semiconductor technology. This invention provides a manner to re-energize the Flash memory array to improve the retention characteristics of the memory without altering the clock cycle determinism of the system. Under certain conditions the Flash memory bit cells will lose their charge/non-charge over time. In this particular FLASH technology, an ECC is used to correct single bit errors within a 32 bit word. If there is time before multiple errors occur within a word, the single error cases are identified and 'ReFlashed' to bring the value of the cell back to its 'newly' programmed levels. This dramatically improves the long term retention characteristics of the memory while requiring some control logic and an area of non-volatile scratch/status information.

Method to extend data retention for flash based storage in a real time device processed on generic semiconductor technology

A math coprocessorincludes a multiply-accumulate unit. Multiplier-accumulate unitincludes a multiplier arrayfor selectively multiplying first and second operands, the first and second operands having a data type selected from the group including floating point and integer data types. An adderselectively performs addition and subtraction operations on third and fourth operands, the third and fourth operands selected by multiplexer circuitry from the contents of a set of associated source registers, data output from multiplier arrayand data output from adder

Math coprocessor

The present invention is a programmable Analog to Digital Converter (ADC) unit () that includes an analog to digital converter (), which includes one or more analog inputs (). The unit () additionally includes a control/status register block (). The unitfurther includes a FIFO register block () with a first, second, third, and fourth FIFO conversion register. Further included is a programmable sequencer () that includes a first (), second (), third (), and fourth () programmable sample sequencer. And further, the unit () includes a first (), second (), third (), and fourth () trigger event control multiplexer, where each trigger event control multiplexer corresponds to each programmable sample sequencer.

Analog to digital converter unit

A system 100 including a central processing unit 101 operates in response to a set of instructions for processing information. A port 134 provides access to selected circuitry forming a part of the system by an external device. A set of non-volatile programmable security elements 136 selectively enable and disable the operation of the interface to provide a private environment for processing the information.

Methods and circuits for securing encached information

A soft cache system compares tag bits of a virtual address with tag fields of a plurality of soft cache register entries, each entry associated with an index to a corresponding cache line in virtual memory. A cache line size for the cache line is programmable. When the tag bits of the virtual address match the tag field of one of the soft cache entries, the index from that entry is selected for generating a physical address. The physical address is generated using the selected index as an offset to a corresponding soft cache space in memory.

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Austin, TX, United States of America

Gregory Allen North