International Business Machines Corporation

Gregory Albert Dancker

Paul E Schardt

Harvey Gene Kiel

Thomas M Armstead

John Elliott Walker

William Van Durrett

William Wyche Plyler

James Albert Pieterick

Edwin C Grazier

Steven Joseph Amell

Bruce Richard Culbertson

Kevin Malachi Galloway

Charles McLees Comp

A simulation system includes glitch injection circuitry in one or more hardware design units to allow the injection of glitches or noise to evaluate the system's response to errors on signals between the hardware design units. The simulation system includes a stimulation module with a set of drivers to input simulation patterns into the design units. Some inputs to software models are driven by the outputs of software models of another design unit. The stimulation module can monitor these signals driven by the software model but it is difficult for the stimulation module to directly drive these signals. The added glitch circuitry allows injection of errors into the simulated hardware by the stimulation module on signals that are not directly driven by the stimulation module but are driven by the outputs of hardware design units.

Simulating and verifying signal glitching

Method and apparatus to simulate and verify signal glitching

A computer system automatically senses characteristics of diverse peripheral devices connected to a common communications port, and automatically maximizes the communications speed with the devices. Coupled in daisy chain fashion to the communications port, all peripheral devices receive every signal issued from the controller port, each device responding only to signals addressed to that device or signals addressed to a universal address. The controller first receives an identifier from peripheral devices attached to the controller port. The controller then interprets the received identifiers to determine a maximum communications speed for each device. Next, the controller and the attached peripheral devices are configured to communicate at the maximum communications speed of the slowest device. This guarantees that all messages sent by the controller are compatible with all peripheral devices. Devices subsequently coupled to the communications port are considered by the controller, and the port and other devices are reconfigured as necessary to ensure the fastest possible communications speed.

Computer system with peripheral device characteristic sensing and

A controller and a properly equipped peripheral device of a computer system easily exchange messages having a compressed data format. Both the controller and the peripheral device are configured to communicate using a predefined basic command set employing a predefined communications format. The controller first verifies that the peripheral device supports a second predefined communications format in addition to the first predefined communications format. Compared to the first format, the second format utilizes messages with greater compression, i.e., an optimized bit stream ('OBS'). The controller next sends the peripheral device a number of commands, including a command of the basic command set accompanied by an OBS enable code. In the case of a write operation, the controller also sends the peripheral device an encoded dataset having the second predefined communications format and representing an underlying unencoded dataset. Although the basic command alone would alert the peripheral device to the transmission of uncompressed data, the presence of the OBS enable code signals a compressed dataset. The peripheral device receives the encoded dataset and, resulting from the received OBS enable code and the command of the basic command set, processes the encoded dataset to obtain the unencoded dataset. In the case of a read operation, the controller receives an encoded dataset, in the second predefined format, from the peripheral device.

Compressed message exchange initiated by basic command accompanied by

Process and apparatus for testing a microprocessor and dynamic RAM by a single tester where the microprocessor and dynamic RAM may be on a single card. The process makes the RAM appear static to an external static tester by separate read/write and refresh logic for the RAM. Two different clock generators connect to logic where each clock is selectively connectable to an on-board oscillator or to an external input. Priority logic for gating the refresh logic within a predetermined interval and gating the read/write logic at other times. The process includes three steps of a static logic test, a memory interface test, and, a functional test of the logic and the dynamic RAM. The third step is accomplished by executing a program in the on-card microprocessor. The three steps of the test form a single set of test data.

Process and apparatus for testing a microprocessor and dynamic ram

Growing community of inventors

Rochester, MN, United States of America

Gregory Albert Dancker