Cisco Technology, Inc.

Microsoft Technology Licensing, LLC

Gregory Alan Bryant

Oded Trainin

Andreas Bernhard Bisplinghoff

Christopher R Fludger

Mohammad Ali Sedaghat

Gary Steven Singer

Embodiments of the present disclosure include techniques for error correction. Multiple successive odd syndromes are generated from input data comprising parity bits. Coefficients are generated and applied to a finite element field to detect multiple bit errors. Error correction circuitry corrects detected error bits. A single bit error detector may detect single bit errors. The error correction circuit may select between a single bit error vector and a multibit error vector based on one of the coefficients. The circuitry may be implemented in combinational logic to perform detection and correction in a single clock cycle.

Error correction systems and methods

A random noise generator for generating a plurality of random noise samples per clock cycle, the noise samples having a distribution. The random noise generator comprises at least a first comparator unit and a second comparator unit, the first comparator unit configured to generate a first plurality of samples representing a high-probability part of the distribution and the second comparator unit configured to generate a second plurality of samples representing a low-probability part of the distribution; and a random selection unit connected to at least the first comparator unit and the second comparator unit. The random selection unit is configured to receive the first plurality of samples generated by the first comparator unit and the second plurality of samples generated by the second comparator unit, to output a random selection of samples from the first plurality of samples and the second plurality of samples.

Random noise generation

To calculate sequential CRCs, a CRC pipeline may be used to calculate the sequential CRCs for a block of data The CRC pipeline includes a plurality of stages, where, in each subsequent stage a CRC calculated from a previous stage is used to calculate an offset CRC. For example, using at least one CRC calculator and CRC shifter, a stage in the pipeline removes an effect of first portion of the data represented by a previously calculated CRC from the CRC and then adds an effect of a second portion of data neighboring the first portion in a received data block to yield an offset CRC. For example, a stage may change CRC(0:63) to CRC(32:95) by removing the effect of bytes 0:31 and adding the effect of bytes 64:95. At each stage, the byte offset may get smaller until all the sequential CRCs have been calculated.

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Raleigh, NC, United States of America

Gregory Alan Bryant