Zenith Electronics Corporation

Zenith Radio Corporation

Gregory A Williams

Wayne E Bretl

Michael Tentler

David L Walker

A dual mode timer circuit has first and second two-input NOR gates with inputs connected to receive a trigger pulse and outputs respectively coupled to first and second RC charging networks. An output NOR gate has its two inputs connected to the RC charging networks respectively, and its output connected to an output terminal. A control input voltage signal is coupled to a fourth NOR gate whose output is connected to control activation of the second RC charging network which has a shorter time constant than the first RC network. The output signal duration is dependent upon which RC network is effective. The output terminal is connected to the other inputs of the first and second NOR gates to render the circuit independent of trigger pulse duration.

Dual-mode timer circuit

A cable television system capable of decoding signals encoded in two different formats, A and B. Format A is identified by digital data on horizontal lines 10-13 in the vertical blanking interval and format B by digital data on horizontal lines 14-17 in the vertical blanking interval. Logic circuitry receives the vertical blanking interval data and supplies one pulse marking the beginning of the vertical blanking interval and an identifier pulse derived from digital data on horizontal lines 13 or 17. A format mode control switch includes a monostable timing circuit producing an output responsive to the vertical blanking interval pulse for a period terminating at approximately horizontal line 14. The timing circuit output is supplied along with the identifier pulse to the inputs of a flipflop for determining which of the decoders A and B is to be energized.

Two mode scrambling system using identifier pulse in vertical blanking

A sync signal separator includes a first monostable flip-flop, connected to be positive-edge triggered and nonretriggerable, with a first timing circuit for generating horizontal output pulses of slightly greater duration than input horizontal sync pulses, a second monostable flip-flop, connected to be negative-edge triggered and nonretriggerable, having a second timing circuit for generating a time duration greater than the normal duration of a vertical sync pulse and an OR gate having inputs coupled to receive input sync pulses and the output of the second monostable flip-flop for controlling the enable input of the second monostable flipflop. The output of the first monostable flipflop produces the horizontal output pulses and the output of the second monostable flipflop produces the vertical output pulses.

Low cost synchronizing signal separator

An addressable subscription television decoder includes an input stage including an IF amplifier for converting a scrambled RF television signal to a composite baseband video signal. The baseband video signal comprises either a nominal sync component or a sync component having suppressed horizontal sync pulses during video fields and having non-suppressed sync pulses during vertical intervals, the vertical intervals also including selected encoded data signals. An AGC voltage for controlling the gain of the IF amplifier is developed by a circuit exhibiting a relatively short time constant whenever the composite baseband video signal is characterized by nominal level sync pulses, the time constant being increased in response to suppressed horizontal sync pulses. The sync pulses produced during the vertical intervals of the composite baseband video signal are thereby not subjected to excessive IF gain for facilitating processing of the data signals by the decoder.

Growing community of inventors

Elk Grove Village, IL, United States of America

Gregory A Williams