Lsi Logic Corporation

Lsi Corporation

Gregory A Johnson

Kunal N Taravade

Travis Alister Bradfield

Robert E Ward

Charles W Jurgensen

Gayle W Miller

Andrew Carl Brown

Tracy Robert Spitler

Matthew Richard Motiff

A system, apparatus and/or method is provided for fabricating an integrated capacitor during the fabrication of a transistor employing chemical mechanical polishing of a gate electrode of the transistor. Components of the integrated capacitor, particularly the lower electrode of a parallel plate capacitor in one form thereof, and an outer plate of a cylindrical-like capacitor in another form thereof, are defined by the polish stop layer during chemical mechanical polishing (CMP) of a gate of the transistor. According to an aspect of the subject invention, the polish stop layer may be an oxide or a nitride.

Method of fabricating an integral capacitor and gate transistor having nitride and oxide polish stop layers using chemical mechanical polishing elimination

An arbitration elimination scheme for a bus. In a preferred embodiment, a programmable counter determines when a SCSI bus idle condition is reached and when a portion of an arbitration window for the bus has passed without participants. If there are no participants for arbitration, the SCSI initiator eliminates arbitration by asserting SEL and issuing initiator/target IDS. If any other device attempts to arbitrate at this time, the device sees SEL asserted and does not attempt to participate in arbitration.

Method for improving selection performance by using an arbitration elimination scheme in a SCSI topology

A silent mirroring protocol is provided, which eliminates the arbitration/selection times associated with all nexuses after the first nexus. During the initial SCSI bus negotiation, the initiator determines the transfer mode capability of all targets. The initiator establishes a group identification. Participants of the group recognize the group and look for an individual identification within the group. The initiator performs arbitration/selection with attention to the leader of the group. The initiator uses a message out phase with a vendor command to select a participant for a data block transfer. Each participant snoops the bus and recognizes when it is the target. If the initiator has more data to mirror, the process is repeated. When the last data block is transferred, the initiator sends a message out to the last participant, which is interpreted by the target leader as a command to release the bus. Each participant reselects the nexus initiator and returns a status.

Method, apparatus, and program for improving data mirroring performance in a SCSI topology

An innovative circuit is disclosed that enhances performance on a SCSI bus by pipelining nexuses in order to associate all nexus attributes on a per nexus basis. For example, a pipeline of nexuses is created so as to associate all of the nexus attributes from different connections involved. A plurality of load stages is provided whereby each load stage can latch all nexus attributes received at that stage. The latched nexus attributes can be loaded and stored at that stage or shifted to the next stage. As a result of the loading and shifting operations, a pipeline of nexuses is created that associates all of the nexus attributes received from the different connections on a per nexus basis. Therefore, all types of data traffic can be processed concurrently on a SCSI bus, which enhances data throughput and bus performance.

Pipeline SCSI nexus associativity circuit

A system and method for implementing logic changes in integrated circuits (ICs). In a preferred embodiment, donor logic elements are taken from donator logic paths. The donated cells are implemented into a logic path altered by an ECO. The donated cell is replaced by spare cells. Timing analysis is done to ensure all logic paths are timing closed.

System and method for achieving timing closure in fixed placed designs after implementing logic changes

The present invention is a method, system, and product for optimizing timing in a circuit after layout of the circuit has been completed. The circuit includes at least one variable delay line and includes coupled endpoint devices. The variable delay line includes multiple, different selectable settings. A current setting of the variable delay line is varied from a maximum setting to a minimum setting. A timing accuracy indicator of a combination of the coupled endpoint devices is determined as the variable delay line is varied from its maximum setting to its minimum setting. Thus, multiple timing accuracy indicators are determined where an indicator is determined for and associated with each one of the settings from the maximum setting to the minimum setting. An optimum one of the selectable settings is determined utilizing the timing accuracy indicators, wherein the optimum one of the settings is associated with an optimum one of the multiple timing accuracy indicators.

Method, system, and product for achieving optimal timing in a data path that includes variable delay lines and coupled endpoints

A confinement device for operative arrangement within a substrate etching chamber, having a lower surface of the device generally arranged over a substrate outer top surface such that a gap-spacing therebetween is generally equidistant. This spacing is less than a sheath thickness for the plasma, preferably less than &#x2153;of an inner width of an aperture through the lower surface of the device. The aperture, sized preferably greater than 3 times the sheath thickness, is in communication with a channel of the device in which an etchant gas can be confined for reaction to selectively etch a localized area in the substrate outer top surface generally below the aperture. A system for dry etching an IC wafer includes a substrate etching chamber and a confinement device. The etchant gas may be a plasma induced and sustained by RF energy, a microwave source, or other source, as designed. And, a method is included for selectively etching a localized area in a substrate outer top surface, having the steps of: arranging a lower surface of a confinement device over the outer top surface, leaving a spacing therebetween, so that an aperture through said lower surface is located generally above the localized area (the spacing may cover the whole of the outer top surface, an area on which microcircuits are fabricated, or some other portion of the outer top surface); and providing an etchant gas to a channel in the device that is in communication with the aperture.

Confinement device for use in dry etching of substrate surface and method of dry etching a wafer surface

An integrated circuit includes a vertical-interdigitated capacitor located between an upper interconnect layer and a lower interconnect layer. Both interconnect layers include conductors formed of a metal capable of atom diffusion or ion migration, such as copper. The capacitor plates contact an interconnect layer conductor to create barrier layers to prevent atom diffusion or ion migration from the conductors at the contact locations. Additional barrier layers contact the conductors at locations other than where the capacitor plate portions contact the conductors, and the additional barrier layers are preferably formed of the same material and at the same time that one of the plates is formed. The integrated circuit may include a via plug interconnect extending between conductors of upper and lower interconnect layers, with a plug barrier layer surrounding the plug material to prevent atom diffusion or ion migration from the plug material.

Encapsulated-metal vertical-interdigitated capacitor and damascene method of manufacturing same

A substantially vertical interdigitated plate capacitor, formed in interlayer dielectric material between upper and lower interconnect layers of conductors in an integrated circuit, comprising a lower plate that has at least one U-shaped portion and a horizontal portion connected to an upper edge of the U-shaped portion. The capacitor's upper plate also has at least one U-shaped portion positioned within the interior of the lower plate's U-shaped portion and a horizontal portion connected to an upper edge of each vertically extending leg. The integrated circuit incorporating the capacitor comprises a via connection having a U-shaped layer extending between the conductors of the relatively upper and relatively lower interconnect layers and is formed simultaneously with one of the U-shaped portions of the capacitor plates.

Vertical interdigitated metal-insulator-metal capacitor for an integrated circuit

A method of fabricating a semiconductor wafer having an active area and an inactive outer clear out area includes the step of fabricating a number of active dies on a first side of the wafer such that each of the number of active dies is completely contained within the active area of the wafer. The method also includes the step of generating a laser beam with a laser device. Moreover, the method includes the step of scribing a code in the inactive outer clear out area of the wafer with the laser beam such that the code is completely contained within the inactive outer clear out area of the wafer. An apparatus for scribing a code in an inactive outer clear out area of a first side of a semiconductor wafer is also disclosed.

Method and apparatus for scribing a code in an inactive outer clear out area of a semiconductor wafer

A method of exposing an alignment mark defined in a first side of a semiconductor wafer includes the step of engaging a second side of the wafer with a wafer chuck. The method also includes the step of positioning the wafer in a chamber having a photochemical reactant gas present therein during the engaging step. Moreover, the method includes the step of impinging laser beams on the first side of the wafer such that a reactant specie is generated from the photochemical reactant gas. Yet further, the method includes the step of removing material from the first side of the wafer with the reactant specie. An apparatus for exposing an alignment mark defined in a first side of a semiconductor wafer is also disclosed.

Method and apparatus for removing residual material from an alignment mark of a semiconductor wafer

A confinement device for operative arrangement within a substrate etching chamber, having a lower surface of the device generally arranged over a substrate outer top surface such that a gap-spacing therebetween is generally equidistant. This spacing is less than a sheath thickness for the plasma, preferably less than &frac13;,of an inner width of an aperture through the lower surface of the device. The aperture, sized preferably greater than 3 times the sheath thickness, is in communication with a channel of the device in which an etchant gas can be confined for reaction to selectively etch a localized area in the substrate outer top surface generally below the aperture. A system for dry etching an IC wafer includes a substrate etching chamber and a confinement device. The etchant gas may be a plasma induced and sustained by RF energy, a microwave source, or other source, as designed. And, a method is included for selectively etching a localized area in a substrate outer top surface, having the steps of: arranging a lower surface of a confinement device over the outer top surface, leaving a spacing therebetween, so that an aperture through said lower surface is located generally above the localized area (the spacing may cover the whole of the outer top surface, an area on which microcircuits are fabricated, or some other portion of the outer top surface); and providing an etchant gas to a channel in the device that is in communication with the aperture.

A vertical plate capacitor is formed in interlayer dielectric material which separates conductors of upper and lower interconnect layers by a method which avoids the accumulation of residual materials from chemical mechanical polishing (CMP). The method comprises the steps of forming a capacitor via into the interlayer dielectric material, forming a first conductive layer having a U-shaped portion into the capacitor via, forming U-shaped capacitor dielectric material in the U-shaped portion of the first conductive layer, forming a second conductive layer having a U-shaped portion in the U-shaped capacitor dielectric material, filling an interior of the U-shaped portion of the second conductive layer with a plug material, and polishing after the capacitor via is entirely occupied by these elements.

Method of forming and electrically connecting a vertical interdigitated metal-insulator-metal capacitor extending between interconnect layers in an integrated circuit

An apparatus for etching a first side of a semiconductor wafer down to a desired level. The apparatus includes an etching chamber. The apparatus also includes a wafer chuck configured to engage the wafer by a second side of the wafer, and position the wafer in the etching chamber. The apparatus also includes a light source unit positioned such that light signals generated by the light source unit are directed into the wafer. Moreover, the apparatus includes a light receiving unit positioned such that the light signals generated by the light source unit emanate out of the wafer and are received with the light receiving unit. The light receiving unit includes a first optical material and a second optical material having an interface therebetween. The first optical material has a linear index of refraction, whereas the second optical material has a nonlinear index of refraction which is dependent on an intensity level of the light signals received with the light receiving unit. The light signals are refracted at the interface if the linear index of refraction of the first optical material does not match the nonlinear index of refraction of the second optical material. A method of etching a first side of a semiconductor down to a desired level is also disclosed.

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Colorado Springs, CO, United States of America

Gregory A Johnson