Hewlett-packard Company

Agilent Technologies, Inc.

Keysight Technologies, Inc.

Gregory A Hill

John H Guilford

Ted B Ziemkowski

Daniel E Yee

Nathan A Berg

Steven Joseph Narciso

Gidget A Cathcart

Lee A Atchison

Raymond A Purcell

Joseph Eugene Mueller

Leslie P Hammer

Charles D Platz

Glen Atkins

Charles Platz

An apparatus that moves stimulus data and response data between a memory and a device under test (DUT) over a plurality of data transfer banks. In a first mode the data transfer banks output the stimulus data to the DUT as respective independent banks of serial stimulus data channels, and write the response data into the memory responsive to data provided as respective independent banks of channels of serial data from the DUT. In a second mode the data transfer banks output the stimulus data to the DUT as a single bank of combined serial stimulus data channels, and write the response data into the memory responsive to the data provided as a combined single bank of channels of serial data from the DUT.

Multi-bank digital stimulus response in a single field programmable gate array

In an instrumentation system, the functionality of an I/O interface which controls an instrument is extended with an I/O interface extension library. The extension library operates to receive a function call and determines whether the function call is supported by the underlying I/O interface. If the function call is supported by the underlying I/O interface, the function call is passed on to the I/O interface for processing. If the function call is not supported by the underlying I/O interface, the function call is decoded into a sequence of standard I/O primitives that are supported by the underlying I/O interface, which are then sent on to the I/O interface for processing. In one embodiment, reduced overall latency time is achieved by packaging multiple sequential functions into a package and sending the package over an I/O bus to the instrument I/O controller as a single unit rather than sending each sequential function using separate bus instructions.

Extension library to standard visa library for support of complex I/O functions

A three port FIFO buffer circuit uses off the shelf static RAM and dedicated shallow, e.g. 16 word, FIFOs in a multi-level caching scheme. The circuit results in multiple, reconfigurable, deep (e.g. up to 32k word) FIFO buffers. The preferred embodiment of the invention provides a buffer that comprises a bank of 32k word RAM, six dual port 16-word FIFOs, and associated sequencing logic. The sequencing logic includes RAM address registers/counter associated with each of the six FIFOs, and manages the movement of data into and out of the RAM.

Multiport data buffer having multi level caching wherein each data port

A bidirectional asynchronous open collector buffer. The buffer employs set delays and control logic to prevent latch up of the buffer when the low signal is applied to one of the ports of the buffer. Additionally, the buffer employs reset delays in conjunction with the control logic for suppressing oscillation of the buffer when one of the ports of the buffer is released from the applied low signal.

Bidirectional asynchronous open collector buffer

A ground return scheme is provided for multiple high speed digital signals that are capacitively coupled between networks, where the networks are connected to different ground planes (i.e. they are isolated) on a common circuit board. A first embodiment of the invention provides a low impedance ground path for each signal crossing the isolation boundary. The ground path is achieved by placing a ground return capacitor proximate to the signal coupled capacitor to substantially minimize the loop area of the total current path. This arrangement substantially minimizes the self inductance of each signal current path and the mutual inductance, i.e. coupling, between signal paths. The arrangement also has the benefit of reducing self-induced voltage drops in each ground return path, thereby reducing crosstalk between the signals, reducing ground bounce (resulting in faster settling times), and also reducing common-mode voltage induced between the grounding systems. Consequently, application of the invention produces improved signal integrity, reduced generation of electromagnetic emissions, and reduced susceptibility to electromagnetic interference. A second embodiment of the invention adds common-mode chokes to each signal-ground pair. The chokes provide a measure of high-frequency isolation between the ground systems, as well as between the various signal paths.

Ground return for high speed digital signals that are capacitively

Methods and associated apparatus for using a dual-boot capable programmable device and for updating programmed information in such a dual-boot capable programmable device. The apparatus of the present invention includes a primary boot memory device, a secondary boot memory device, and means for selecting between the two memory devices for purposes of 'booting' the dual-boot mode device. In particular, a reset switch of the apparatus of the present invention resets devices in the dual-boot capable programmable device and is coupled to a selection device. The selection device multiplexes signals from the two boot memory devices onto the corresponding bus signals of the dual-boot capable programmable device. When a 'long' reset switch activation is sensed, the selection device selects a first of the two boot memory devices for coupling to the programmable device. A 'short' activation of the reset switch selects the other boot memory device. The present invention also includes methods for updating the contents of the two boot memory devices so as to avoid an inoperable state encountered due to failure of the update process in a single boot memory device. In particular, both boot memory devices are updated in sequence. The second memory update is prevented if the first memory update is determined to have failed.

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Loveland, CO, United States of America

Gregory A Hill