Intel Corporation

Georgia Tech Research Corporation

Gregorio R Murtagian

Kuang C Liu

Zhichao Zhang

Kemal Aygun

Hong Xie

Srikant Nekkanty

Sanka Ganesan

Fay Hua

Joshua Heppner

Jeffory L Smalley

Donald Tiendung Tran

Michael J Hill

Sriram Srinivasan

Gaurav Chawla

David J Llapitan

Ting Zhong

Jonathan W Thibado

Feroz Mohammad

Alan C McAllister

Bhanu Jaiswal

Amit Abraham

Robert L Sankman

Omkar G Karhade

Nitin A Deshpande

Saikumar Jayaraman

Zhiguo Qian

George Vergis

William J Lambert

Kaladhar Radhakrishnan

Russell S Aoki

Xiang Li

Ram S Viswanath

Rajasekaran Swaminathan

Ralph V Miele

Dimitrios Ziakas

Bassam N Coury

Thomas A Boyd

Yidnekachew S Mekonnen

Jeff C Morriss

Brent S Stone

Xiaoqian Li

Eric W Buddrius

Steven A Klein

Chong J Zhao

Vijaykumar Krithivasan

Todd R Coons

Mani Prakash

Yu Zhang

John M Lynch

Wesley Brook Morgan

Karumbu Meyyappan

Eduard Roytman

Divya Pratap

Rolf Laido

Thomas T Holden

Daniel Neumann

Martin Rodriguez

Vanessa Smet

Omkar Gupte

An electronic device carrier structure can include a substrate including a plurality of electrical contacts spaced apart on the substrate, a plurality of electrically conductive balls, each of the electrically conductive balls being on a respective one of the plurality of electrical contacts, solder attaching each of the electrically conductive balls to respective ones of the electrical contacts to form an attachment boundary where the solder ends on a surface of each of the plurality of electrically conductive balls, and a polymer layer extending on the substrate onto the plurality of electrically conductive balls to form a surface of the polymer layer at a contact point on the plurality of electrically conductive balls that is above the attachment boundary and below an apex of each of the plurality of electrically conductive balls.

Electronic device carrier structures including polymer layers as barriers to solid state solder diffusion and methods of forming the same

Embodiments disclosed herein include photonics packages and systems. In an embodiment, a photonics package comprises a package substrate, where the package substrate comprises a cutout along an edge of the package substrate. In an embodiment, a photonics die is coupled to the package substrate, and the photonics die is positioned adjacent to the cutout. In an embodiment, the photonics package further comprises a receptacle for receiving a pluggable optical connector. In an embodiment, the receptacle is over the cutout.

Package expanded beam connector for on-package optics

Embodiments disclosed herein include assemblies. In an embodiment, an assembly comprises a socket and a bolster plate on a board, where the bolster plate has load studs and an opening that surrounds the socket; a shim having first and second ends; and a carrier on the bolster plate, where the carrier has an opening and cutouts. The shim may have an opening through the first end as the second end is affixed to the carrier. The opening of the shim entirely over one cutout from a corner region of the carrier. In an embodiment, the assembly comprises an electronic package in the opening of the carrier, where the electronic package is affixed to the carrier, and a heatsink over the electronic package and carrier, where the first end is directly coupled to a surface of the heatsink and a surface of one load stud of the bolster plate.

Socket load regulation utilizing CPU carriers with shim components

A microelectronics package, comprising a substrate comprising a first bondpad and a second bondpad over a dielectric. An inductor comprising at least one wire extends over the dielectric. The at least one wire has a first end coupled to the first bondpad and a second end coupled to the second bondpad, and an inductor core layer over the dielectric. The inductor core layer comprises a magnetic material. At least a portion of the inductor extends within the inductor core layer.

Wirebond and leadframe magnetic inductors

Embodiments include a transmission line-land grid array (TL-LGA) socket assembly, a TL-LGA socket, and a package substrate. The TL-LGA socket assembly includes a TL-LGA socket having an interconnect in a housing body, the interconnect includes a vertical portion and a horizontal portion. The housing body has a top surface and a bottom surface, where the top surface is a conductive layer. The TL-LGA socket assembly also includes a package substrate having a base layer having a signal pad and a ground strip. The base layer is above the conductive layer of the housing body of the TL-LGA socket. The ground strip is above the horizontal portion of the interconnect and adjacent to the signal pad. The horizontal portion is coupled to the signal pad on the base layer. The package substrate may have a pad with a reduced pad area.

Selective ground flood around reduced land pad on package base layer to enable high speed land grid array (LGA) socket

An electronic device may include a semiconductor package, that may include a package substrate. The package may include a semiconductor die. A plurality of package interconnects may include a first pillar extending from a surface of the package substrate. The electronic device may include a socket that may be configured to couple with the semiconductor package. The socket may include a plurality of socket interconnects configured to engage with the package interconnects. The plurality of socket interconnects may include a first contact, and the first contact may include an arm. The arm of the first contact may be configured to engage with the first pillar, and the arm may be configured to laterally displace when engaged with the first pillar. The engagement of the arm with the first pillar may establish an electrical communication pathway between the semiconductor package and the socket.

Pillar based socket

High-speed data transmissions through a CPU socket are facilitated with CPU socket contacts that have a CPU socket contact body that improves bandwidth throughput. The CPU socket contact body is partially suspended from a CPU socket contact and may include a cavity. The CPU socket contact body includes capacitive impedance that substantially cancels an inductive impedance of the CPU socket contact. Canceling the inductive impedance causes the CPU socket contact to operate like an impedance-matched coaxial transmission line, which enables better bandwidth throughput than a non-impedance matched transmission line.

CPU socket contact for improving bandwidth throughput

A vertically ground isolated package device can include (1) ground shielding attachment structures and shadow voiding for data signal contacts; (2) vertical ground shielding structures and shield fencing of vertical data signal interconnects; and (3) ground shielding for an electro-optical module connector of the package device. These reduce cross talk between data signal contacts, attachment structures and vertical 'signal' interconnects of the package device. The ground shielding attachment structures may include patterns of solder bumps and/or surface contacts. The shadow voiding may be surrounding voids in ground planes that are larger than the data signal solder bumps. The vertical ground shielding structures may include patterns of ground shield interconnects between the vertical data signal interconnects: The shield fencing may include patterns of ground plated through holes (PTH) and micro-vias (uVia). The ground shielding for the electro-optical module may include patterns of ground isolation shielding attachments and contacts.

Rlink-ground shielding attachment structures and shadow voiding for data signal contacts of package devices; vertical ground shielding structures and shield fencing of vertical data signal interconnects of package devices; and ground shielding for electro optical module connector data signal contacts and contact pins of package devices

Embodiments of the present disclosure are directed towards techniques and configurations to provide solder contacts for electrical connection in socket assemblies. In one embodiment, a solder contact may be disposed on the bottom surface of a die package such that the solder contact is conductively coupled to electrical contacts of the die package. The solder contacts may be disposed to be coupled to pins of a socket assembly, to provide conductive coupling of the electrical contacts of the die package and the pins of the socket assembly. The solder may be selected to be sufficiently soft to provide for better electrical conduction. The pins may also be configured to penetrate the solder contact to provide for better electrical conduction. Other embodiments may be described and/or claimed.

Solder contacts for socket assemblies

Embodiments of the present disclosure are directed towards an inductor structure having one or more strips of conductive material disposed around a core. The strips may have contacts at a first end and a second end of the strips, and may be disposed around the core with a gap between the contacts. The inductor structure may be mounted on a surface of a substrate, and one or more traces may be formed in the surface of the substrate to electrically couple two or more of the strips of conductive material to one another to form inductive coils. Other embodiments may be described and/or claimed.

Surface-mount inductor structures for forming one or more inductors with substrate traces

An apparatus comprises a cable connector including: a first connector body portion including a first plurality of electrical contacts arranged to contact electrical contacts of a first surface of an edge connector substrate; a second connector body portion separate from the first connector body portion and including a second plurality of electrical contacts arranged to oppose the first plurality of electrical contacts of the first connector body portion and to contact electrical contacts of a second surface of the edge connector substrate, wherein the first and second plurality of electrical contacts are electrically coupled to one or more cables; and a joining mechanism configured to join the first connector body portion and the second connector body portion together and to apply a bias force to the edge connector substrate when the edge connector substrate is arranged between the first connector body portion and the second connector body portion.

Universal linear edge connector

Configurable central processing unit (CPU) package substrates are disclosed. A package substrate is described that includes a processing device interface. The package substrate also includes a memory device electrical interface disposed on the package substrate. The package substrate also includes a removable memory mechanical interface disposed proximately to the memory device electrical interface. The removable memory mechanical interface is to allow a memory device to be easily removed from the package substrate after attachment of the memory device to the package substrate.

CPU package substrates with removable memory mechanical interfaces

An electronic device connection system includes a first electrical device and a second electrical device. The first electrical device includes a plurality of electrical connectors disposed in, on, or about at least a portion of an exterior surface of the first electrical device. The second electrical device includes a plurality of electrical contacts disposed in, on, or about at least a portion of an exterior surface of the second electrical device. A mechanical compressor exerts a force on at least one of the first electrical device or the second electrical device such that the electrical connections on the first electrical device physically and conductively couple to the electrical contacts on the second electrical device. The device casing may function as the mechanical compressor. The electrical connectors and/or electrical contacts may include injection molded connectors that include a conductive material dispersed in a thermoplastic matrix.

Small form factor sockets and connectors

Growing community of inventors

Phoenix, AZ, United States of America

Gregorio R Murtagian