Intel Corporation

Gregor Stellpflug

Sebastian Winkel

Ethan Schuchman

Jaroslaw Topp

Naveen Neelakantam

David Pardo Keppel

Joshua B Fryman

Arun Raman

Polychronis Xekalakis

Allan Douglas Knies

Patrick P Lai

Tyler N Sondag

John H Kelm

Denis M Khartikov

Demos Pavlou

Rainer Theuer

Rakesh Ranjan

Ulrich Bretthauer

Rainer Theur

Mirem Hyuseinova Seidahmedova

Methods and apparatuses relating to assigning a logical thread to a physical thread. In one embodiment, an apparatus includes a data storage device that stores code that when executed by a hardware processor causes the hardware processor to perform the following: translating an instruction into a translated instruction, assigning a logical thread for the translated instruction, and providing a thread map hint for the translated instruction; and a hardware scheduler to assign a physical thread of the hardware processor to execute the logical thread based on the thread map hint.

Apparatuses and methods to assign a logical thread to a physical thread

Various different embodiments of the invention are described including: (1) a method and apparatus for intelligently allocating threads within a binary translation system; (2) data cache way prediction guided by binary translation code morphing software; (3) fast interpreter hardware support on the data-side; (4) out-of-order retirement; (5) decoupled load retirement in an atomic OOO processor; (6) handling transactional and atomic memory in an out-of-order binary translation based processor; and (7) speculative memory management in a binary translation based out of order processor.

Apparatus and method for efficiently implementing a processor pipeline

A system includes a processor with a front end to receive an instruction stream reordered by a software scheduler and including a plurality of memory operations and alias information indicating how a given memory operation may be evaluated. Furthermore, the processor includes a hardware scheduler to reorder, in hardware, the instruction stream for out-of-order execution. In addition, the processor includes a calculation module to determine, for a given memory operation and based upon the alias information, a checking range of memory atoms subsequent to the given memory operation and a virtual order of the memory operation. The virtual order indicates an original ordering of the instructions. The processor also includes an alias unit to reorder the instruction stream, determine whether the hardware reordering caused an error, and determine whether the software reordering caused an error based upon the checking range and the virtual order.

Instruction and logic for memory disambiguation in an out-of-order processor

Growing community of inventors

Braunschweig, Germany

Gregor Stellpflug