Panasonic Corporation

Apple Inc.

Gregoire J Le Grand De Mercey

Richard W D Booth

Gilbert H Herbeck

Toru Matsuura

Koji Takinami

Paul Cheng-Po Liang

Richard B Booth

Saleh Osman

Hua Wang

Jung Wan Kim

Yair R Koren

An apparatus is disclosed in which a clock signal may propagate through a delay circuit. The delay circuit may include a first and a second delay stage, in which each delay stage may be programmable for one of two delay times, depending on a value of a respective control signal to each delay stage. The delay circuit may also include circuitry which may change the value of the respective control signal from a first value to a second value. The circuitry may change the value of the respective control signal responsive to a determination that an output of the first stage and an output of the second stage are equal.

Glitch less delay circuit for real-time delay adjustments

Various embodiments of a clock generator are disclosed. An example system may include a functional unit, and a clock generation unit configured to adjust a frequency of an output clock signal responsive to an assertion of an enable signal from the functional unit. The clock generation unit may also be configured to halt the output clock signal responsive to a de-assertion of the enable signal by the functional unit and to restart the output clock signal responsive to a determination that a first predetermined amount of time has elapsed since the output clock signal was halted. The clock generation unit may be further configured to adjust the frequency of the output clock signal responsive to restarting the output clock signal, and to halt the output clock signal responsive to a determination that the frequency of the output clock signal is within a predetermined frequency range that includes the target frequency.

Method for calibrating a clock signal generator in a reduced power state

In one embodiment, the present invention includes a transmitter having a baseband, a multiplexer, a digital-to-analog converter unit, and/or a Chireix combiner. The baseband transmits components of an in-phase signal and a quadrature-phase signal to the multiplexer. The multiplexer generates a first signal and/or a second signal which have a phase difference which matches only a single predetermined phase difference. The single predetermined phase difference should be selected to ensure that the Chireix combiner is optimized for efficiency. Thus, a phase of the first signal or the second signal can have a phase of the in-phase signal or the quadrature-phase signal to ensure that the phase difference between the second signal and the first signal matches only the single predetermined phase difference. The Chireix combiner receives the first analog signal and the second analog signal.

Efficient cartesian transmitter using signal combiner

A phase interpolation circuit based on injected passive capacitances and an inductance for forming a resonator. The circuit conducts at least a first reference signal having a first phase component and a second reference signal having a second phase component shifted from the first phase component. By selectively switching the first reference signal and/or the second reference signal through one or more capacitances, an interpolated third signal having a third phase component between the first phase component and the second phase component can be generated. An inductor is connected with one or more of the capacitances for forming a resonant circuit to boost the signal level of the interpolated third signal. By utilizing resonance, an improved signal-to-noise ratio may be obtained for the interpolated third signal. An additional amplification stage, secondary to the resonant circuit, may be incorporated for further amplifying the signal level of the interpolated third signal.

Phase interpolator based on an injected passive RLC resonator

The digital RF transmitter includes a decoder for receiving the in phase (I) and quadrature (Q) digital baseband signals, a phase generator for generating eight waveforms at a carrier frequency where each phase is a multiple of 45 degrees, a first set of main amplifiers of fixed output power, a second set of auxiliary amplifiers of fixed output power such that the ratio of the voltage amplitudes at the outputs of the second set of auxiliary amplifiers to the voltage amplitudes at the outputs of the first set of main amplifiers is fixed at sqrt(2)&#x2212;1, and a set of multiplexers for selecting one of the eight carrier waveforms, or an off signal, to transmit to each of the first set of main amplifiers and the second set of auxiliary amplifiers based on both the in phase (I) digital baseband signal and the quadrature (Q) digital baseband signal.

Digital RF transmitter optimized for linear quantized IQ up conversion

A low cost high-efficiency all-digital transmitter using all-digital power amplifiers ('DPA') and various mapping techniques to generate an output signal, which substantially reproduces a baseband signal at a carrier frequency. A baseband signal generator generates a baseband signal which is quantized by a signal processor using a quantization map. A DPA control mapper outputs control signals to phase selectors using the quantized signal and a quantization table. Each phase selector receives one of the control signals and outputs a waveform at a carrier frequency with a phase corresponding to the control signals, or an inactive signal. Each DPA in a DPA array has an assigned weight, receives one of the waveforms from the phase selectors, and outputs a power signal according to the weight of the DPA and the phase of the received waveform. The combined power signal substantially reproduces the baseband signal at the carrier frequency.

High-efficiency all-digital transmitter

The disclosed embodiments provide method and apparatus for digital to analog conversion of a signal that may be limited to a bandpass frequency. In an exemplary embodiment, a bandpass DAC is disclosed which includes a plurality of gates. Each gate receives a carrier signal and one of a plurality of input bits of a digital data. A combiner network is provided which includes a plurality of lossless elements corresponding to each of the plurality of gates. The combiner network receives the gate outputs and provides a digitally weighted signal. A resonating element connected to the combiner network resonates the combiner network and provides a filtered output signal which is linearly combined.

Growing community of inventors

San Francisco, CA, United States of America

Gregoire J Le Grand De Mercey