Unisys Corporation

Other

Greggory D Donley

Manoj Gujral

Paul N Israel

Laurence P Flora

David Edgar Castle

A network node for receiving a packet of data written from the network and providing the packet to the network. The packet of data includes first data received from the network in response to a first clock signal and second data provided to the network in response to a second clock signal. The node is adapted to compensate for a drift between the first clock signal and the second clock signal. The node includes a first counter that receives the first clock signal and produces a write-point signal in response to the first clock signal. The node also includes a plurality of registers arranged in a wrap-around configuration, with a first one of the registers coupled to be selected by the write-point signal to receive the first data from the network. A second counter receives the second clock signal and produces a read-point signal in response to the second clock signal, with a further register being selected by the read-point signal to provide the second data to the network. A comparison block receives the read-point signal and the write-point signal and compares the read-point signal and the write-point signal to detect the drift between the first clock signal and the second clock signal, and generates an output signal representing the drift. A control block receives the output signal from the comparison block and generates a signal to the second counter to adjust the read-point signal to compensate for the drift between the first and the second clock signals.

Resynchronization of data

A multi-clock pulse synchronizer circuit with and IN-section receiving and storing prescribed in-pulses and input clock signals and responsively outputting intermediate pulses; and an OUT-section for receiving and storing the intermediate pulses, synchronous with certain output clock signals and processing them to generate certain output-signals, for better avoiding metastability.

Methods to avoid instability

A method of arranging and operating a cache in a multi-processor computer system with N local processors, where a requesting device can request a cycle to be issued, where the method involves 'posting' the 'cycles', while also storing information for completing a cycle in a Queue and causing the requesting device to be issued 'termination' immediately, rather than waiting for the cycle to reach its destination.

Method for cycle request with quick termination without waiting for the

A multi-level distributed data processing system includes: 1) a system bus having a main memory coupled thereto; 2) multiple high level cache memories, each of which has a first port coupled to the system bus and a second port coupled to a respective processor bus; and, 3) each processor bus is coupled to multiple digital computers through respective low level cache memories. Further, each low level cache memory stores data words with respective tag bits which identify each data word as being shared, modified or invalid but never exclusive; and, each high level cache memory stores data words with respective tag bits which identify each data word as being shared, modified, invalid, or exclusive. By identifying a data word in a low level cache memory as shared, even when that data word is not in any other low level cache memory, the high level cache memories are able to prevent two computers on separate processor busses from modifying that data word differently; and in addition, the high level cache memories are able to track the data words which get modified.

Method and circuitry for modifying data words in a multi-level

In a multiprocessor computer system where a number of 'agents' can compete for access to a 'resource', a method of ameliorating 'Livelock' and preventing any such agent from being unduly frustrated from such access, this method comprising: arranging the system to include an arbitrating unit and a common system bus connecting a number of processors, plus an Avoidance unit included in each processor and including a Random-Number generator and automatic 'Random Backoff' that causes an agent that fails to secure access to wait for one or more given random time periods T.sup.B before reattempting such access, with each said time period T.sup.B being provided by the random number generator so as to likely differentiate from competing agents.

Livelock avoidance

In a multiprocessor computer system where a number of 'agents' can compete for access to a 'resource', a method of ameliorating 'Livelock' and preventing any such agent from being unduly frustrated from such access, this method comprising: arranging the system to include an arbitrating unit and a common system bus connecting a number of processors, plus an Avoidance unit included in each processor and including a Random-Number generator and automatic 'Random Backoff' that causes an agent that fails to secure access to wait for one or more given random time periods T.sub.B before reattempting such access, with each said time period T.sub.B being provided by the random number generator so as to likely differentiate from competing agents.

Random delay subsystems

An array of digital data processing nodes arrayed in at least one node-ring where each node has its own transmission-clock which is approximately the same frequency as the transmission-clock of other nodes in the ring and where data is transferred in data-packets, the combination therewith of data-transmission-resynchronizing stage comprising a 'circular FIFO' arrangement.

Data resynchronization

Described are techniques to stabilize storage devices receiving signals from plural asynchronous docks, especially to avoid 'metastability', in particular, a multi-dock pulse synchronizer circuit with an IN-section for receiving and storing prescribed impulses and input cock signals, and for responsively outputting intermediate signals: and an OUT-section for receiving and storing the intermediate pulses, synchronous with certain output clock signals and processing them to generate certain output-signals which avoid metastability.

Avoiding instability

An array of Digital data processing nodes are shown arrayed in at least one node-ring where each node has its own transmission-clock which is approximately the same frequency as the transmission-clock of other nodes in the ring and where data is transferred in data-packets, combined with this is a data-transmission-resynchronizing stage featuring 'circular FIFO' arrangement.

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Sunnyvale, CA, United States of America

Greggory D Donley