Hewlett-packard Development Company, L.p.

Agilent Technologies, Inc.

Pmc-sierra, Inc.

Gregg S Goyins

Robert J Lawton

Narayan Rao Ayalasomayajula

Jonathan Sadowsky

John R McVey

A method and system for controlling multiple client access to cache memory and a single CAM device. Each client has a corresponding integrity controller in communication with the CAM device and all the other integrity controllers associated with the other clients in the system. Each integrity controller monitors states of the other clients, and inhibits its respective client from executing any operation when a common lookup index is detected during a co-pending operation with a first client. Once the operations of the first client are completed, its integrity controller signals the integrity controller of other clients to exit their inhibit or hold states, thereby allowing the other clients to resume their operations. Another advantage of the integrity controller is that its algorithms also prevents multiple host memory fetches of the same key, thereby saving time and improving system performance.

Multi-client content addressable memory access control method

The invention is directed towards high performance switchable polarizers for optical projection displays. One embodiment of the invention is a switchable polarizer with (1) two conductive electrodes and (2) a liquid crystal material that is positioned between the two conductive electrodes. The electrodes apply a uniform electric field across the liquid crystal material when one of the electrodes is placed at a first potential and other electrode is placed at a second potential different from the first potential. These two electrodes also heat the liquid crystal material when they conduct current. When equal currents are drawn through the electrodes, the electrodes apply a uniform electric field across the liquid crystal during a heating operation.

High performance switchable polarizers for optical projection displays and circuits for driving the polarizers

One embodiment of the invention is a digital filter that avoids image flicker in a projection display that has two operational modes. This digital filter avoids undesired intensity variations between successive frames by changing all the assigned pixel values by the same amount during either of the two modes. This digital filter typically only needs to correct some of the least significant bits ('LSB's') of the pixel values during either operational mode. This is because the dynamic range of the flicker is often very limited (e.g., it is often less than 5%). In fact, some embodiments combine the flicker-filtering function with the dither-control function, if the correction of a LSB causes an over correction of the flicker problem.

Method and apparatus for avoiding image flicker in an optical projection display

An error detection system for detecting errors in data output from a FIFO memory includes a first CRC generator for receiving an inbound data stream and generating a first CRC value based on a data block in the inbound data stream. A device coupled to the first CRC generator selectively inputs the data block and the first CRC value into the FIFO. A second CRC generator generates a second CRC value based on the data block after being output from the FIFO in an outbound data stream. The second CRC value indicates whether the data block contains an error.

Error detection system for a FIFO memory

Some embodiments of a data channel that interleaves read and write access to a frame buffer include a bit-plane storage device, a single frame buffer, a data controller and a digital pixel display. Transferring data through the single frame buffer by interleaving reads and writes includes (1) alternately writing to the frame buffer and reading from the frame buffer portions of each bit-plane of a sequence bit-plane data; and (2) writing to said frame buffer so as to replace each said portion of a bit-plane in the frame buffer with a corresponding portion of a next bit-plane. By interleaving read and write accesses, a single frame buffer and less interface logic are necessary to transfer data from a storage device to a digital pixel display. In a three channel digital color pixel imaging device, this reduces the number of frame buffer SDRAM units from six to three, and significantly reduces the overall cost associated with implementing data flow through the data storage and frame buffer blocks.

Method and apparatus for interleaving read and write accesses to a frame buffer

One embodiment of the invention is a digital filter that avoids image flicker in a projection display that has two operational modes. This digital filter avoids undesired intensity variations between successive frames by changing all the assigned pixel values by the same amount during either of the two modes. This digital filter typically only needs to correct some of the least significant bits (&ldquo;LSB's&rdquo;) of the pixel values during either operational mode. This is because the dynamic range of the flicker is often very limited (e.g., it is often less than 5%). In fact, some embodiments combine the flicker-filtering function with the dither-control function, if the correction of a LSB causes an over correction of the flicker problem.

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Rocklin, CA, United States of America

Gregg S Goyins