Lattice Semiconductor Corporation

Gregg R Josephson

Ju Shen

Chan-Chi Jason Cheng

Roy D Darling

Mark E Bauer

John E Turner

Douglas H Bower

David L Tennant

A sense amplifier for sensing the impedance between two terminals includes an amplification stage whose input is connected to one of the terminals. The input is connected to a power supply voltage VCC through two transistors in parallel. One transistor provides a high speed by providing a large current when the voltage on the input is low. Moreover, to increase speed and save power, that transistor turns off when the amplification stage input voltage is slightly above the amplification stage trip voltage. The other transistor provides a small current to pull the amplification stage input up almost to VCC to reduce the amplification stage power consumption. The small current does not interfere significantly with the pull-down speed. One of the amplification stage power terminals is connected to ground through current limiting transistors to reduce the amplification stage power consumption when the amplification stage input voltage is at its low value which is slightly below the trip voltage. A reference voltage generator controls one of the two transistors connecting the amplification stage input to VCC so as to prevent the low value of the amplification stage input voltage from converging to the trip voltage over a wide range of the VCC and processing variations.

Sense amplifiers and sensing methods

A structure and method for in-system programming of a programmable logic device are provided. The in-system programming structure provides one dedicated pin for in-system programming function, additional in-system programming pins are multiplexed with programmable input/output pins used in functional operations. When an enable signal is received at the dedicated pin, the multiplexed pins relinquish their roles as programmable input/output pin to become in-system programming pins. A state machine controls the programming steps. The in-system programming structure can be cascaded in a 'daisy chain' fashion.

Structure and method for multiplexing pins for in-system programming

A single poly EE cell and an array using said cell, with the array being provided electrical connections such that the select gate for the read select transistor and the select gate for the write select transistor may be separately controlled. In the array, first level metal is utilized for connection to the gates of the read and write select transistors and second level metal is utilized for connection to the product term connections of the cell.

Single poly EE cell with separate read/write paths and reduced product

The apparent voltage used to program an EEPROM cell is increased by applying a negative voltage to the memory control gate of the sense transistor in the cell. This method is applicable to devices in which the substrate is negatively biased.

Method of programming electrically erasable programmable read-only

A non-volatile, erasable and programmable interconnect cell which includes a pass transistor, a select transistor, and a floating gate transistor wherein a voltage applied to the pass transistor is drawn from a common connection between the floating gate transistor and the select transistor.

Non-volatile erasable and programmable interconnect cell

A programmable logic array is disclosed employing arrays of electrically erasable and programmable cells. The device includes a dual purpose programming circuit which is employed to provide programming data to the AND array to program the AND array cells, and to provide OR array row selection data during OR array programming, thereby eliminating the need for a separate OR array row decoder. A method and apparatus is also disclosed for efficiently testing the AND array cells and input circuitry by bulk stripe programming the array cells.

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Aloha, OR, United States of America

Gregg R Josephson