Microchip Technology Inc.

Intel Corporation

Cerebrum Holding Corporation

Itt Manufacturing Enterprises, Inc.

Corrent Corporation

Gregg Lahti

Joseph W Triece

Rodney J Pesavento

Steven Dawson

Peter Munguia

Aditya Katragada

Matthew Hoppes

Brandon Sleater

Michael Howell

Richard J Takahashi

D C Sessions

Lee Noehring

R Vaughn Langston

Techniques are described for providing consistent memory operations and security across electronic circuitry components having disparate memory and/or security architectures when integrating such disparately architected components within a single system, such as a system on chip. A programmable logical hierarchy of isolated memory region (IMR) enforcement circuits is provided to protect such IMRs, allowing or preventing memory access requests from one of multiple distinct circuitry components based on configuration registers for the IMR enforcement circuits. Integration of multiple trust domain architectures associated with the multiple distinct circuitry components is facilitated via trust domain conversion bridge circuitry that includes translation logic for generating information in accordance with a first trust domain architecture based on information provided in accordance with a distinct second trust domain architecture.

Integration of disparate system architectures using configurable isolated memory regions and trust domain conversion bridge

A client device presents a user interface including a macro entry field for defining a macro indicator from a plurality of macro indicators and transmits the macro indicator. A server stores a database of macro-based diagnoses, each macro-based diagnosis associated with one or more elements of an accession, and one or more specimens associated with the accession. The server also receives the macro indicator from the client device, retrieves an initial diagnosis from the database of macro-based diagnoses responsive to the macro indicator, and transmits the initial diagnosis. The client device, receives the initial diagnosis, pre-populates one or more text boxes on the user interface with information from the initial diagnosis, and enables the user to edit the pre-populated one or more text boxes.

Macro-based diagnoses for anatomic pathology

A microcontroller may have a central processing unit (CPU); a programmable logic device receiving input signals and having input/outputs coupled with external pins, and an interrupt control unit receiving at least one of the internal input signals or being coupled with at least one of the input/outputs and generating an interrupt signal fed to the CPU.

Microcontroller with configurable logic array

A system has at least one bus, a central processing unit (CPU) coupled with the bus, a memory coupled with the bus, a direct memory access (DMA) controller having a plurality of DMA channels and operating independently from the CPU and being coupled with the bus, wherein for access to the bus the DMA controller is programmable in a first mode to have priority over the CPU and in a second mode in which at least one DMA channel of the DMA controller is suspended from accessing the bus.

Direct memory access controller

A cache module for a central processing unit has a cache control unit with an interface for a memory, a cache memory coupled with the control unit, wherein the cache memory has a plurality of cache lines, at least one cache line of the plurality of cache lines has an address tag bit field and an associated storage area for storing instructions or data, wherein the address tag bit field is readable and writeable and wherein the cache control unit is operable upon detecting that an address has been written to the address tag bit field to initiate a preload function in which instructions or data from the memory are loaded from the address into the at least one cache line.

Configurable cache for a microprocessor

A microcontroller or integrated system has a bus, a plurality of peripheral devices each one coupled with the bus, a non-volatile memory, and a state machine coupled with the non-volatile memory and being operable to initialize the peripheral devices by reading initialization information from the non-volatile memory and writing it to the peripheral devices.

Dynamic state configuration restore

A cache module for a central processing unit has a cache control unit coupled with a memory, and a cache memory coupled with the control unit and the memory wherein the cache memory has a plurality of cache lines, each cache line having a storage area for storing instructions to be issued sequentially and associated control bits, wherein at least one cache line of the plurality of cache lines has at least one branch trail control bit which when set provides for an automatic locking function of the cache line in case a predefined branch instruction has been issued.

A cache module for a central processing unit has a cache control unit coupled with a memory, and a cache memory coupled with the control unit and the memory, wherein the cache memory has a plurality of cache lines, at least one cache line of the plurality of cache lines has an address tag bit field and an associated storage area for storing instructions to be issued sequentially and at least one control bit field, wherein the control bit field is coupled with the address tag bit field to mask a predefined number of bits in the address tag bit field.

A system for processing a data packet to determine if a replay condition exists for the data packet, wherein the data packet comprises a sequence number for comparison to a highest sequence number. The processing system includes a mask register to store a mask value, wherein the mask value provides an indication of prior receipt by the system of a plurality of data packets, and a shifter comprising an input coupled to receive the mask value from the mask register, wherein the shifter is operable to shift a binary value by a number of bit positions, the number determined by a difference between the sequence number and the highest sequence number.

System and method for anti-replay processing of a data packet

A full-adder post processor performs modulo arithmetic. The full-adder post processor is a hardware implementation able to calculate A mod N, (A+B) mod N and (A&#x2212;B) mod N. The processor includes a full adder able to add the operands A and B while modulo reduction is accomplished in the processor by successively subtracting the largest possible multiple of the modulus N obtainable by bit shifting prior to subtraction.

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Gilbert, AZ, United States of America

Gregg Lahti